{"title":"Semi-adaptive distributed approach for triplet-based architecture inter-core communication Network-on-Chip","authors":"Karim Soliman, Chunfeng Li, Shi Feng","doi":"10.1016/j.vlsi.2025.102489","DOIUrl":null,"url":null,"abstract":"<div><div>Network-on-Chip (NoC) architectures offer significant performance improvements over traditional bus-based systems. However, as NoC designs become more complex, congestion within channels and buffers can degrade performance. Efficient routing algorithms are essential to mitigate congestion and optimize overall NoC performance. This study examines Triplet-Based Architecture (TriBA) architecture and its baseline deterministic shortest-path routing algorithm. The deterministic nature of this algorithm, combined with TriBA’s inherent characteristics, may exacerbate congestion and lead to routing deadlocks, particularly in high-traffic nodes. This work introduces a novel two-stage semi-adaptive routing algorithm to address congestion within TriBA-NoC. The proposed approach leverages congestion levels within downstream buffers of TriBA sub-level apex vertices as an additional routing metric solely at the source node. The primary goal of the proposed strategy is to alleviate congestion, specifically at hot nodes, which in turn leads to reduced communication latency, shorter queuing times in downstream buffers, lower power consumption, and an enhancement in overall network throughput. Comprehensive simulations utilizing gem5-HeteroGarnet have substantiated the effectiveness of the proposed semi-adaptive routing for TriBA-NoC. The approach yields a significant decrease in latency (up to 31.71%), and a decline in buffer queuing time, with reductions reaching 43.14%. Additionally, it enhances throughput by 6.28% and lowers downstream buffer power consumption by an average of 12.15% across various traffic patterns when compared to baseline algorithms. These improvements are evident in practical workloads, as demonstrated by simulations using the PARSEC benchmark suite, which reveal latency reductions between 0.91% and 45.86%. Nonetheless, these performance enhancements are accompanied by a modest power overhead, estimated at approximately 3.94%.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102489"},"PeriodicalIF":2.5000,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025001464","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Network-on-Chip (NoC) architectures offer significant performance improvements over traditional bus-based systems. However, as NoC designs become more complex, congestion within channels and buffers can degrade performance. Efficient routing algorithms are essential to mitigate congestion and optimize overall NoC performance. This study examines Triplet-Based Architecture (TriBA) architecture and its baseline deterministic shortest-path routing algorithm. The deterministic nature of this algorithm, combined with TriBA’s inherent characteristics, may exacerbate congestion and lead to routing deadlocks, particularly in high-traffic nodes. This work introduces a novel two-stage semi-adaptive routing algorithm to address congestion within TriBA-NoC. The proposed approach leverages congestion levels within downstream buffers of TriBA sub-level apex vertices as an additional routing metric solely at the source node. The primary goal of the proposed strategy is to alleviate congestion, specifically at hot nodes, which in turn leads to reduced communication latency, shorter queuing times in downstream buffers, lower power consumption, and an enhancement in overall network throughput. Comprehensive simulations utilizing gem5-HeteroGarnet have substantiated the effectiveness of the proposed semi-adaptive routing for TriBA-NoC. The approach yields a significant decrease in latency (up to 31.71%), and a decline in buffer queuing time, with reductions reaching 43.14%. Additionally, it enhances throughput by 6.28% and lowers downstream buffer power consumption by an average of 12.15% across various traffic patterns when compared to baseline algorithms. These improvements are evident in practical workloads, as demonstrated by simulations using the PARSEC benchmark suite, which reveal latency reductions between 0.91% and 45.86%. Nonetheless, these performance enhancements are accompanied by a modest power overhead, estimated at approximately 3.94%.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.