Integration-The Vlsi Journal最新文献_第6页

Chaos-based authentication of encrypted images under MQTT for IoT protocol 物联网协议下MQTT加密图像的混沌认证

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-02-07 DOI: 10.1016/j.vlsi.2025.102378

José David Rodríguez-Muñoz , Esteban Tlelo-Cuautle , Luis Gerardo de la Fraga

{"title":"Chaos-based authentication of encrypted images under MQTT for IoT protocol","authors":"José David Rodríguez-Muñoz , Esteban Tlelo-Cuautle , Luis Gerardo de la Fraga","doi":"10.1016/j.vlsi.2025.102378","DOIUrl":"10.1016/j.vlsi.2025.102378","url":null,"abstract":"<div><div>In lightweight cryptographic applications, the authentication of encrypted data is a challenge that can be solved by using high-order chaotic systems. The proposed work shows that increasing the length of bits in a Hash function, leads to diminish the possibility of a collision. Using high-order chaotic systems, can also lead to use large prime numbers by exploiting the fact that the division and modulo operations provide a better distribution in a most uniform way. In addition, because a prime number has factors including 1 and himself, then this greatly reduces the appearance of repetitive patterns in a modulo operation. In this manner, this article presents the implementation of a chaos based system for authentication of encrypted RGB images using Raspberry Pi devices. First, a two dimensional (2D) map, and 3D, and 4D chaotic systems, are implemented on Raspberry Pi devices to design pseudo-random number generators (PRNG). Second, the randomness of the sequences is evaluated by performing NIST (National Institute of Standards and Technology) tests. Third, the random sequences are used to construct a stream cipher and an authenticated Hash function based on a method called pseudo dot product. Fourth, RGB images are encrypted using the PRNGs based on 2D, 3D, and 4D chaotic systems. In the proposed work, all these processes are performed under a machine-to-machine (M2M) wireless connectivity system, which is available on the message queuing telemetry transport (MQTT) communication protocol for Internet of Things (IoT). In the experiments, three Raspberry Pi devices are configured as a publisher, a broker, and a subscriber to work on MQTT for sending and receiving encrypted RGB images, while the images are authenticated through the evaluation of Hash function tags, which are generated by using 2D, 3D, and 4D chaotic systems. The main conclusion is that the encryption/decryption and authentication processes are much better when using high-dimensional chaotic systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102378"},"PeriodicalIF":2.2,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143372516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Intra-class CutMix data augmentation based deep learning side channel attacks 基于深度学习的类内CutMix数据增强侧信道攻击

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-02-01 DOI: 10.1016/j.vlsi.2025.102373

Runlian Zhang , Yu Mo , Zhaoxuan Pan , Hailong Zhang , Yongzhuang Wei , Xiaonian Wu

{"title":"Intra-class CutMix data augmentation based deep learning side channel attacks","authors":"Runlian Zhang , Yu Mo , Zhaoxuan Pan , Hailong Zhang , Yongzhuang Wei , Xiaonian Wu","doi":"10.1016/j.vlsi.2025.102373","DOIUrl":"10.1016/j.vlsi.2025.102373","url":null,"abstract":"<div><div>CutMix data augmentation can provide a large amount of augmented data for DL-SCA (deep learning side channel attacks) by generating new power traces. However, traces generated by CutMix may lose dependency with the new label, which may reduce the accuracy of the training model. In light of this, we propose an improved intra-class CutMix data augmentation method. Firstly, the original traces are classified by the label. Then, the original traces are selected by the same label constraint to generate new traces according to CutMix, which can ensure the dependency between the generated trace and its label. Furthermore, in order to maintain balance among different classified datasets, the traces are generated sequentially according to distinct labels. Finally, based on the augmented traces, the Multilayer Perceptron (MLP) and Convolutional Neural Network (CNN) models can be constructed and trained to recover the key of AES. In order to verify the effectiveness of the proposed method, we conduct experimental evaluations using the MLP and CNN models based on DPA-contest v4 dataset and ASCAD dataset. The test results show that the traces generated with the intra-class CutMix method can be very similar to the original traces, and the MLP and CNN models can be effectively trained based on the generated traces to recover the key of AES. Besides, compared with existing data augmentation methods, the proposed method can complete secret key recovery with faster convergence and fewer traces.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102373"},"PeriodicalIF":2.2,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance analysis of 4:1 MUX APUF Architecture Implemented on Zynq 7000 SoC FPGA 4:1 MUX APUF架构在zynq7000 SoC FPGA上的性能分析

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-02-01 DOI: 10.1016/j.vlsi.2025.102379

Kaveri Hatti, C. Paramasivam

{"title":"Performance analysis of 4:1 MUX APUF Architecture Implemented on Zynq 7000 SoC FPGA","authors":"Kaveri Hatti, C. Paramasivam","doi":"10.1016/j.vlsi.2025.102379","DOIUrl":"10.1016/j.vlsi.2025.102379","url":null,"abstract":"<div><div>Physical unclonable functions (PUF) are a type of physical system that harvests data from integrated circuits fragile physical components. These systems offer a highly secure way to generate cryptographic keys for cryptographic operations and protect secure IPs from threats, manipulation, and duplication due to their un-clonability properties. Prior literature has designed various Arbiter PUFs with 2:1 MUX, but they consume a large area to generate the larger response bits. Based on our literature survey, this is the first paper to design an Arbiter PUF with 4:1 MUX, which reduces the area overhead. This paper utilizes a 4:1MUX APUF design is implemented on 10 ZYNQ-7000 SoC FPGA devices using the LUT6 primitive to overcome the challenge of designing an unbiased PUF architecture on the FPGA device. The study also presents two different methodologies to generate responses for the corresponding challenge of 4:1 MUX Arbiter PUF. The design showed a uniqueness rate of 49 % when evaluated on both methodologies. The dependability percentages for temperature fluctuations (20–70 °C) were 99 %. Finally, the performance parameter of the proposed PUF is state-of-the-art.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102379"},"PeriodicalIF":2.2,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Language semantics to support secure computation and communication in embedded systems via hardware monitors 通过硬件监视器在嵌入式系统中支持安全计算和通信的语言语义

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-02-01 DOI: 10.1016/j.vlsi.2025.102367

Garett Cunningham , Siqin Liu , Harsha Chenji , David Juedes , Avinash Karanth

{"title":"Language semantics to support secure computation and communication in embedded systems via hardware monitors","authors":"Garett Cunningham , Siqin Liu , Harsha Chenji , David Juedes , Avinash Karanth","doi":"10.1016/j.vlsi.2025.102367","DOIUrl":"10.1016/j.vlsi.2025.102367","url":null,"abstract":"<div><div>As embedded systems with manycores and Network-on-Chips (NoCs) become ubiquitous, emerging hardware and software vulnerabilities have made it challenging to ensure system integrity especially when third-party intellectual property (IP) is used for rapid prototyping. Prior works have evaluated hardware monitors for ensuring correctness of the system by threat assessment and effective mitigation. However, none have evaluated models that combine both computation (processor pipeline) and communication (NoC) vulnerabilities simultaneously. In this paper, we propose a high-level policy language called d-GUARD that is used to define runtime security policies that can be compiled into hardware monitors. The advantage of this new language is the ability to dynamically change policies based on program’s runtime behavior. To translate high-level policies into low-level hardware monitors, we describe a compiler for d-GUARD that synthesizes policies into Verilog modules. Instead of simply evaluating the design of secure policies for processor pipelines, we extend to secure NoC microarchitectures, including policies for links and routers, as well as policies to prevent Denial-of-Service (DoS) attacks. To mitigate attacks against secure microarchitectures, we also propose fault-tolerant routing approaches to avoid rogue routers when the number of policy violations exceeds a certain threshold. Our secure policies for processor pipelines and NoC microarchitectures consume marginal area and power overhead when compared to baseline making it well suited for low-cost embedded systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102367"},"PeriodicalIF":2.2,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143288596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A wide-input-range boost converter with three-phase self-start and adaptive zero current detector for photovoltaic energy harvesting 一种具有三相自启动和自适应零电流检测器的宽输入范围升压变换器，用于光伏能量收集

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-02-01 DOI: 10.1016/j.vlsi.2025.102376

Hao Wang, Ping Luo, Xiangwen Xin, Yunze Li

引用次数: 0

Lossless grounded capacitance multipliers using two CFOAs and a grounded capacitor 使用两个cfoa和一个接地电容的无损接地电容乘法器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-31 DOI: 10.1016/j.vlsi.2025.102375

Tolga Yucehan

{"title":"Lossless grounded capacitance multipliers using two CFOAs and a grounded capacitor","authors":"Tolga Yucehan","doi":"10.1016/j.vlsi.2025.102375","DOIUrl":"10.1016/j.vlsi.2025.102375","url":null,"abstract":"<div><div>Two new lossless grounded capacitance multipliers (GCMs) are proposed, in which a grounded capacitor and two current-feedback operational amplifiers (CFOAs) are used. Nevertheless, two floating resistors are used in the proposed GCMs. The proposed GCMs consist of three passive components. Thus, the proposed GCMs are obtained with a minimal quantity of passive components. The proposed GCMs have a high operating frequency range at a high multiplying factor. Identical passive component requirements are not needed in the proposed GCMs. In addition, the proposed GCMs can be controlled electronically by using the current-controlled current conveyor with a buffer instead of the second CFOA. However, there is no investigation on electronic tunability in this study. 0.18 μm CMOS technology parameters are employed for the CFOAs used in the proposed lossless GCMs. The layout area of the CFOA is 978.75 μm<sup>2</sup>. All simulations are performed with the SPICE program. In all simulations, supply voltages of the CFOA are selected as ±1.25 V. The simulation results verified the theoretical results from about 30 Hz to 3 MHz. The simulation results show that temperature changes do not affect the proposed GCMs much. The proposed circuits consume 1.91 mW power. In addition, the GCMs in this paper are used in the first-order active low-pass filter, and experiments of these circuits are achieved with AD844s, which are commercial devices for the CFOAs. Also, the experimental results confirm the theoretical results from about 2.5 kHz to 1 MHz.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102375"},"PeriodicalIF":2.2,"publicationDate":"2025-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

CMOS multifunctional structure, with applications in analog signal processing CMOS多功能结构，具有模拟信号处理方面的应用

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-31 DOI: 10.1016/j.vlsi.2025.102377

Cosmin Radu Popa

引用次数: 0

156 dB low-voltage low-power CMOS exponential function generator circuit 156db低压低功耗CMOS指数函数产生电路

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-31 DOI: 10.1016/j.vlsi.2025.102363

Cosmin Radu Popa

引用次数: 0

Extrinsic calibration of complex machine vision system for mobile robot 移动机器人复杂机器视觉系统的外部标定

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-31 DOI: 10.1016/j.vlsi.2025.102370

Ruben Alaniz-Plata , Fernando Lopez-Medina , Oleg Sergiyenko , Wendy Flores-Fuentes , Julio C. Rodríguez-Quiñonez , Cesar Sepulveda-Valdez , José A. Núñez-López , David Meza-García , José Fabián Villa-Manríquez , Humberto Andrade-Collazo , Vera Tyrsa

{"title":"Extrinsic calibration of complex machine vision system for mobile robot","authors":"Ruben Alaniz-Plata , Fernando Lopez-Medina , Oleg Sergiyenko , Wendy Flores-Fuentes , Julio C. Rodríguez-Quiñonez , Cesar Sepulveda-Valdez , José A. Núñez-López , David Meza-García , José Fabián Villa-Manríquez , Humberto Andrade-Collazo , Vera Tyrsa","doi":"10.1016/j.vlsi.2025.102370","DOIUrl":"10.1016/j.vlsi.2025.102370","url":null,"abstract":"<div><div>Autonomous mobile robots are essential in industry, logistics, and service applications, such as infrastructure inspection, where navigation in dark and narrow environments is one of the most challenging tasks. This project presents the design and development of a patented artificial vision system for a mobile robot, which combines a high-precision laser scanner and a stereo-vision system. The objective is to enhance the robot’s surface scanning capabilities in complex environments. The proposed methodology allows to determine the relative position between systems to integrate data of the laser scanner with stereo-vision cameras and inertial sensors, providing robust and accurate environmental perception that enables the characterization of ventilation ducts surface. Experimental results show a mean correspondence error of <span><math><mrow><mn>7</mn><mo>.</mo><mn>4515</mn><mspace></mspace><mi>mm</mi></mrow></math></span> in absolute terms for the combined data.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102370"},"PeriodicalIF":2.2,"publicationDate":"2025-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143288287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

O.O: Optimized one-die placement for face-to-face bonded 3D ICs O.O .优化了面对面键合3D集成电路的单模放置

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-31 DOI: 10.1016/j.vlsi.2025.102371

Xingyu Tong , Yuhao Ren , Zhijie Cai , Peng Zou , Min Wei , Yuan Wen , Zhifeng Lin , Jianli Chen

{"title":"O.O: Optimized one-die placement for face-to-face bonded 3D ICs","authors":"Xingyu Tong , Yuhao Ren , Zhijie Cai , Peng Zou , Min Wei , Yuan Wen , Zhifeng Lin , Jianli Chen","doi":"10.1016/j.vlsi.2025.102371","DOIUrl":"10.1016/j.vlsi.2025.102371","url":null,"abstract":"<div><div>As the miniaturization of integrated circuits (ICs) reaches its physical limits, the industry is entering a “more-than-Moore” era, demanding new Electronic Design Automation (EDA) tools. Existing TSV-based 3D placers focus on minimizing cuts while burgeoning F2F-bonded ICs feature dense interconnection between two planar die. Towards this novel structure, we proposed an integrated adaptation methodology upon mature one-die-based placement strategies. First, we instructively utilized a one-die placer to provide a statistical looking-ahead net diagnosis. The netlist henceforth shall be coarsened topologically and geometrically using a multi-level framework. Our multi-objective gain formulation guides a level-by-level refinement of the partition. This formulation considers factors like cut expectation, heterogeneous row heights, and balanced cell distribution, enabling efficient incremental calculations at each level. Given the partition, we synchronized the behavior of analytical planar placers by balancing the density and wirelength objective function among asymmetric layers. Finally, the result will be further improved by heuristic detail placement of bonding terminals and a post-place partition adjustment. Experimental results demonstrate that our fine-grained fusion of partitioning and placement techniques are competitive compared with the top three winners of the 2022 ICCAD CAD Contest, achieving the best normalized average wirelength with competitive runtime under various 3D architectural constraints.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102371"},"PeriodicalIF":2.2,"publicationDate":"2025-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143419457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0