Integration-The Vlsi Journal最新文献

{"title":"Hop-CIM: An all-digital two-level approximate SRAM-CIM macro for high energy-efficient HNN acceleration with data-aware early exit and column-wise partial-sum reuse","authors":"Shunqin Cai ,&nbsp;Liukai Xu ,&nbsp;Wentao Liu ,&nbsp;Dengfeng Wang ,&nbsp;Keqing Ouyang ,&nbsp;Jinyu Wang ,&nbsp;Weizhong Wu ,&nbsp;Qiang Huang ,&nbsp;Zhi Li ,&nbsp;Yanan Sun","doi":"10.1016/j.vlsi.2025.102525","DOIUrl":"10.1016/j.vlsi.2025.102525","url":null,"abstract":"<div><div>Hopfield Neural Networks (HNNs) have emerged as a promising paradigm for image restoration tasks with the inner associative memory properties to corrupted image reconstruction. However, traditional HNN accelerators relying on full-precision vector-matrix multiplication (VMM) operations introduce significant computational redundancy, as the binary state updates process of HNNs depend solely on the sign of VMM results rather than their precise values. To address this inefficiency, Hop-CIM, an all-digital approximate SRAM-based computing-in-memory (SRAM-CIM) macro, is proposed for energy-efficient HNN acceleration. The key innovation points of the proposed Hop-CIM include: (1) a two-level approximation strategy that fully exploits the error-tolerant characteristics of HNNs, (2) a data-aware threshold-based early exit mechanism during tile-by-tile partial-sum accumulation, and (3) a partial-sum reuse method with column-wise weight matrix compression. The combined effect of (2) and (3) reduces the redundant multiply-and-accumulate (MAC) operations by 55.7 %. Experimental results demonstrate that under 28 nm technology node, the proposed Hop-CIM macro delivers 1591<em>TOPS/W</em> energy efficiency with 1-bit/1-bit input/weight quantization, outperforming the traditional full-precision SRAM-CIM design with 1-bit/3-bit input/weight quantization and the approximate SRAM-CIM design with 1-bit/1-bit input/weight quantization by 7.72x and 2.48x, respectively. In addition, Hop-CIM achieves 0.944 in structural similarity index measure (<em>SSIM</em>) for 28 × 28 image restoration.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102525"},"PeriodicalIF":2.5,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144924944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Area-efficient architectures of Midori lightweight block cipher for resource constrained devices","authors":"Chaitanya Kella ,&nbsp;Pulkit Singh ,&nbsp;Zeesha Mishra ,&nbsp;Bibhudendra Acharya","doi":"10.1016/j.vlsi.2025.102501","DOIUrl":"10.1016/j.vlsi.2025.102501","url":null,"abstract":"<div><div>The practise of tiny computing and embedded devices in Internet of Things (IoT) has brought up severe security trepidations in information security. Providing secured end-to-end communication in Resource Constrained Environment (RCE) with limited hardware is challenging task. Over the past few year, Lightweight Cryptography has been recognized as top-notch for gratifying the requirements of RCE. Several lightweight cryptographic algorithms have been proposed for different applications in RCEs. In this paper, Midori block cipher has been chosen to fulfil the objective. Midori block cipher has been area and speed optimized using unconventional serial architectures and memory address scheduling technique. This paper presents two serial architectures M1 and M2 for 64 and 128-bit block size respectively. The proposed designs are implemented in verilog Hardware Descriptive Language (HDL) using Xilinx Integrated Synthesis Environment (ISE) Design suite and power analysis has been done. The hardware implementation is carried on Field Programmable Gate Array (FPGA). Comparison of the proposed designs has been done on different families of FPGA. The proposed designs has shown a percentage improvement of 38.54% and 36.12% in terms of area for 64 and 128-bit block size respectively. Similarly, the percentage improvement for efficiency is 80.18% and 210.41%, for throughput is 10.69% and 98.13% for 64 and 128-bit block size respectively on FPGA Spartan 6 platform comparing with state-of-the-art Midori cipher.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102501"},"PeriodicalIF":2.5,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144890347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and analysis of VDIBA-based chaotic oscillators and their applications in communication system","authors":"Kushal Kumar ,&nbsp;Akshay Rana ,&nbsp;Shireesh Kumar Rai ,&nbsp;Bhawna Aggarwal","doi":"10.1016/j.vlsi.2025.102518","DOIUrl":"10.1016/j.vlsi.2025.102518","url":null,"abstract":"<div><div>This paper presents three new implementations of Chua's chaotic oscillator using the voltage differencing inverting buffered amplifier (VDIBA). The first implementation replaces the active nonlinear resistor in the classical third-order Chua's circuit with a single VDIBA and two resistors. The second implementation substitutes the bulky passive inductor with a compact VDIBA-based active inductor realized using two VDIBAs and a capacitor. Finally, a sinusoidal oscillator based chaotic oscillator implementation using VDIBAs is explored. A non-ideal analysis is conducted to assess the practical feasibility of the proposed chaotic system. A comprehensive analysis is presented, including bifurcation diagrams, Lyapunov exponents, Routh stability criteria, and basins of attraction determining stability of the proposed circuits. Numerical simulations in MATLAB and circuit simulations in LTspice, using 0.18 μm CMOS TSMC technology parameters, validate the proposed designs. A comparative analysis with existing literature highlights the advantages of the proposed implementations. The experimental results of the proposed chaotic oscillators are presented to validate the theoretical analysis. Furthermore, the potential application of the proposed design in secure chaotic transmission and reception for both analog and digital signals is demonstrated, showcasing the system's high reliability and security through the non-recoverability of the message signal under small parameter variations. Additionally, bit error rate (BER) versus signal to noise ratio (SNR) performance is evaluated under both AWGN and Rayleigh fading conditions to validate the robustness of the communication system.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102518"},"PeriodicalIF":2.5,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144893248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Resource-efficient hardware architecture for low-light image enhancement","authors":"Sidharth Kashyap,&nbsp;Pushpa Giri,&nbsp;Ashish Kumar Bhandari","doi":"10.1016/j.vlsi.2025.102521","DOIUrl":"10.1016/j.vlsi.2025.102521","url":null,"abstract":"<div><div>This manuscript introduces a pipelined and resource-optimized hardware architecture for enhancing dark images with a better gain using a Logarithmic operator which can be auto-tuned by log-average luminance. In the beginning of this architecture, two stage convolutions are used to remove the noise and preserve the details of the images. This convolution operation is optimized through the use of an efficient buffering architecture, carefully tuned convolution coefficients, and a pipelined architecture, which collectively minimize resource consumption. This architecture employs a resource efficient and precise digit-recurrence-based technique for logarithmic calculations. Furthermore, logarithmic number system (LNS) is used to optimize the luminance enhancement module. The LNS reduces the cost of adaptation parameter implementation and simplifies complex arithmetic operations. Resource reutilization is employed to further optimize the adaptation parameter. These optimization results in a significant decrease in the usage of resources such as LUTs, registers, BRAM, and digital signal processors (DSP). This architecture can process low-light HD video with a good quality assessment parameter.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102521"},"PeriodicalIF":2.5,"publicationDate":"2025-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144916962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Implementation of two new 10-bit 1 GS/s hybrid DACs with a novel gain error calibration technique","authors":"Razieh Ghasemi,&nbsp;Mohammad Azim Karami","doi":"10.1016/j.vlsi.2025.102516","DOIUrl":"10.1016/j.vlsi.2025.102516","url":null,"abstract":"<div><div>This paper presents two novel low-power 10-bit hybrid digital-to-analog converters (DACs): ground-connected-ladder DAC (GCL-DAC) and Vdd-connected-ladder DAC (VCL-DAC). The proposed hybrid DACs benefit from a combination of differential resistor ladders and current sources. By utilizing this combination, the number of unit current cells and the complexity of decoders are considerably reduced. Moreover, the proposed hybrid DACs consist of 21 unit current cells and a 6-bit differential resistor ladder, significantly reducing the area and power consumption. A background calibration method is also used to correct the gain error and provide a full swing in the output of both hybrid DACs. The static and dynamic performance of the two proposed DACs is also compared. The proposed DACs are post-layout simulated in 65 nm CMOS technology. The GCL-DAC and VCL-DAC consume 10.98 mW and 9.71 mW of power with a 1.2 V supply voltage. The static specifications of the Integral-Non-Linearity (INL) and Differential-Non-Linearity (DNL) for both DACs are below 0.9 LSB and 0.4 LSB, respectively. Furthermore, the occupation area for GCL-DAC and VCL-DAC is 0.021 mm² and 0.026 mm², respectively. Moreover, both structures are robust against process variations and work properly at the temperature ranges of −40 to 80 °C.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102516"},"PeriodicalIF":2.5,"publicationDate":"2025-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144890348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Post-training quantization for efficient FPGA-based neural network acceleration","authors":"Oumayma Bel Haj Salah ,&nbsp;Seifeddine Messaoud ,&nbsp;Mohamed Ali Hajjaji ,&nbsp;Mohamed Atri ,&nbsp;Noureddine Liouane","doi":"10.1016/j.vlsi.2025.102508","DOIUrl":"10.1016/j.vlsi.2025.102508","url":null,"abstract":"<div><div>The widespread success of Convolutional Neural Networks (CNNs) in computer vision has been accompanied by soaring computational demands, often requiring high-performance GPUs for real-time inference. However, such hardware is impractical in embedded and resource-constrained environment. To address this, we propose a post-training quantization (PTQ) framework that converts CNN models from FP32 to INT8 without retraining, optimized for FPGA deployment. Using asymmetric quantization and TensorFlow Lite, we implemented VGG16 and ResNet50 on a PYNQ-Z1 Field-Programmable Gate Arrays (FPGA). The quantized VGG16 achieved a 67% increase in throughput (from 150 FPS to 250 FPS), a 68% reduction in latency, and a 52% improvement in Power-Delay Product. ResNet50 saw over 420% gain in DSP efficiency, a 3100% increase in LUT efficiency, and a 94% PDP reduction. Despite a marginal accuracy loss, both models showed significantly improved energy efficiency and performance-per-resource utilization. Our results confirm that PTQ enables scalable, low-power AI inference suitable for real-time applications on edge and embedded systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102508"},"PeriodicalIF":2.5,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144860298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ESegNet-ILT: An end-to-end mask optimization method in VLSI design flow based on enhanced SegNet","authors":"Hui Xu ,&nbsp;Yong Xue ,&nbsp;Yu Zhang ,&nbsp;Xia Sun ,&nbsp;Jiale Li ,&nbsp;Ruijun Ma ,&nbsp;Huaguo Liang ,&nbsp;Zhengfeng Huang","doi":"10.1016/j.vlsi.2025.102512","DOIUrl":"10.1016/j.vlsi.2025.102512","url":null,"abstract":"<div><div>With the advancement of technology, the critical dimensions of integrated circuits continue to shrink, leading to an increasing mismatch between the photolithography system and feature sizes. As a result, mask optimization has become a key challenge in the design process of very large-scale integrated circuits (VLSI). In recent years, resolution enhancement technology (RET) and inverse lithography technology (ILT) have been widely used in the field of optical proximity correction (OPC). However, when using inverse lithography technology (ILT) for mask optimization, there are still high computational costs, and the mask's printability is not ideal. To address these issues, this paper proposes ESegNet-ILT, an end-to-end learning-based OPC method. Built on an improved version of SegNet, this approach incorporates convolutional attention modules and multi-scale feature extraction modules, and then incorporates traditional ILT for fine-tuning and refinement to generate higher-quality masks. By introducing convolutional attention block and multi-scale feature extraction module. The model effectively integrates rich feature information across different scales and focuses more on the key features of the target layout, enabling it to generate better initial mask solutions. These initial solutions are then refined through ILT fine-tuning to produce mask with higher printability. Experimental results demonstrate that this method achieves better mask printability and robustness, while reducing bridging defects in printed image. Compared to the state-of-the-art methods, the proposed method reduces the process variation band (PVB) by 15 % while ensuring comparable squared L2 error, and accelerates the turnaround time (TAT) by 2.47 times.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102512"},"PeriodicalIF":2.5,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144852772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of a new compact multiplier-less memtranstor emulator and its application in neuromorphic and chaos generation","authors":"Manoj Kumar ,&nbsp;Shireesh Kumar Rai ,&nbsp;Bhawna Aggarwal ,&nbsp;Maneesha Gupta","doi":"10.1016/j.vlsi.2025.102511","DOIUrl":"10.1016/j.vlsi.2025.102511","url":null,"abstract":"<div><div>This paper presents a compact configuration of memtranstor (MT), a new memory element having direct relation between magnetic flux (φ) and charge (q). The proposed configuration offers a simple architecture as it is designed without the need of any multiplier or any other complex component. This emulator has been realized by employing one operational transconductance amplifier (OTA), one current differencing transconductance amplifier (CDTA), and one voltage differencing current conveyor (VDCC) along with a few passive components. The emulator captures the fundamental relationship between φ and q, enabling the realization of distinctive pinched hysteresis loops under sinusoidal excitation, a hallmark of memtranstive behavior. It is designed to operate at a supply voltage of ±1.25 V. The circuit offers tunability through the variation in biasing voltages ensuring flexibility for a wide range of applications. The accuracy and dynamic characteristics of the proposed architecture are verified through mathematical analysis and LTSpice simulations with a 180 nm CMOS model. To assess the behavior of the proposed emulator in real environment, process-voltage-temperature analysis has been carried out followed by the designing of full custom layout in an area of 4464.88 μm². Furthermore, non-ideal analysis has been carried out considering the parasitic elements at various terminals of the blocks employed in the circuit design. Additionally, to prove the practical feasibility of the proposed circuit, its operation has been confirmed by macro-models of the designated ICs followed by the bread-board implementation using commercial ICs under ±12 V supply voltage. To demonstrate practical utility, the emulator is employed in two key applications: an artificial synapse for neuromorphic systems and a nonlinear chaotic oscillator, both showcasing its relevance for next-generation memory-driven analog computing. The proposed design stands out due to its low component count, compact design, and ease of integration, making it a promising candidate for emerging fields like neuromorphic engineering and chaos-based systems. Furthermore, it provides valuable insights for future research in MT-based nonlinear dynamics and holds significant potential for advancing MT driven applications in neuromorphic computing and beyond.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102511"},"PeriodicalIF":2.5,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144885521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"WF-SPR: A weighted single fanout approach for signal probability-based reliability estimation","authors":"Yue Xiang,&nbsp;Zhen Wang","doi":"10.1016/j.vlsi.2025.102507","DOIUrl":"10.1016/j.vlsi.2025.102507","url":null,"abstract":"<div><div>With continuous improvement of circuit integration, the circuit fault rate has increased. Consequently, accurately and efficiently analyzing and predicting circuit reliability has become a critical objective in digital integrated circuit design. In recent years, as approximate computing circuits (AACs) are getting closer to practical applications, evaluating their reliability has become particularly important. Whether in conventional circuits or AACs, the signal correlation problem caused by fanout nodes can affect the accuracy of circuit reliability evaluation. Moreover, precise reliability evaluation algorithms often come with high computational costs. In this paper, we propose a reliability evaluation method for conventional circuits considering the weight of single fanout nodes based on the signal probability reliability (SPR) method. Meanwhile, this paper improves the method and proposes a new reliability analysis method for AACs. Experimental results on circuits in the ISCAS85 and EvoApprox8b library show that the proposed method has good accuracy and scalability. On both conventional circuits and AACs, the two proposed methods achieve an average error rate of 1% with a time overhead of 0.1% compared to the Monte Carlo (MC) method. On conventional circuits, the average error rate is reduced by 76% compared to the SPR method, and the time overhead is reduced by 97% compared to the SPR multi-pass (SPR-MP) method.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102507"},"PeriodicalIF":2.5,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144893316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient lattice-based Mordell elliptic curve S-box for secure lightweight cryptography","authors":"M.G. Abbas Malik ,&nbsp;Muhammad Hussain ,&nbsp;Zia Bashir","doi":"10.1016/j.vlsi.2025.102505","DOIUrl":"10.1016/j.vlsi.2025.102505","url":null,"abstract":"<div><div>A key focus in research publications on data encryption algorithms is the Substitution Box (S-Box), a fundamental component. Recently, a predominant approach for S-box generation involves utilizing Mordell elliptic curves, chosen for their high security with small key space attributes. However, prevalent S-box algorithms derived from these ECs exhibit structural and algorithmic limits, rendering them less adept for deployment in small devices and lightweight cryptography applications due to elevated running time complexities and less key space. We present a novel approach to overcome these challenges and craft an S-box suitable for compact devices. Our proposed lattice ordering-based S-box algorithm is designed with efficiency and dynamism in mind, employing a Mordell EC as its foundation. A noteworthy aspect of our methodology involves the expedited generation of elements within the Mordell EC, utilizing an efficient method instead of the conventional group law, and constructing the S-box through lattice ordering applied to these elements, which provides <span><math><mrow><mi>p</mi><mo>−</mo><mn>1</mn></mrow></math></span> key size and S-Boxes for any prime <span><math><mrow><mi>p</mi><mo>≡</mo><mn>2</mn><mspace></mspace><mo>mod</mo><mspace></mspace><mn>3</mn></mrow></math></span>. This study aims to overcome existing limitations by introducing an alternative S-box with enhanced algorithmic complexity and reduced computation time compared to existing models based on the Mordell elliptic curve. The proposed method generates <span><math><mrow><mi>p</mi><mo>−</mo><mn>1</mn></mrow></math></span> S-box for a prime <span><math><mrow><mi>p</mi><mo>≡</mo><mn>2</mn><mspace></mspace><mo>mod</mo><mspace></mspace><mn>3</mn></mrow></math></span>, achieves strong cryptographic properties with numerical results: nonlinearity (NL) of 106, differential approximation probability (DAP) of 0.0391, linear approximation probability (LAP) of 0.1328, strict avalanche criterion (SAC) of 0.4958. These results demonstrate superior or comparable performance to contemporary models, making the design well-suited for constrained environments such as IoT and lightweight cryptography applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102505"},"PeriodicalIF":2.5,"publicationDate":"2025-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144810199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}