{"title":"Chaos-based approaches to data security: Analysis of incommensurate fractional-order Arneodo chaotic system and engineering application on a microcomputer","authors":"Akif Akgül , Mustafa Yaz , Berkay Emi̇n","doi":"10.1016/j.vlsi.2025.102355","DOIUrl":"10.1016/j.vlsi.2025.102355","url":null,"abstract":"<div><div>In this study, the Arneodo chaotic system was designed as an incommensurate fractional-order system, and the equilibrium points, time series, and phase portraits of the system were obtained, while the Lyapunov exponents were calculated. The incommensurate fractional-order system was modeled and simulated on the Nvidia Jetson AGX Orin, and its practical applications were realized with the designed electronic circuit. The chaotic equations were discretized via the Grünwald–Letnikov method, and a random number generator (RNG) based on an embedded system was implemented using the proposed algorithm. The RNG successfully met the criteria of international statistical evaluations, including NIST 800-22, FIPS 140-1, and ENT, thereby serving as a foundation for encryption and steganography algorithms. An original image encryption algorithm based on an embedded system was developed using the incommensurate fractional-order chaotic RNG. Encryption algorithm performance was evaluated through various security analyses, demonstrating the success of the incommensurate fractional-order Arneodo (IFOAR) system in embedded encryption applications. Furthermore, an embedded system-based image steganography algorithm was developed using the designed RNG, providing two-level security. The effectiveness of incommensurate chaotic system in steganography applications has been proved by various security analyses.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102355"},"PeriodicalIF":2.2,"publicationDate":"2025-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143288595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A high isolation 16–19 GHz down-conversion mixer in 0.18-μm SiGe Bi-CMOS","authors":"Jun-Da Chen, Shan-Yi Cheng","doi":"10.1016/j.vlsi.2025.102358","DOIUrl":"10.1016/j.vlsi.2025.102358","url":null,"abstract":"<div><div>This paper introduces a novel down-conversion mixer chip explicitly designed for low-orbit satellites operating in the K-band frequency range (16–19 GHz). The chip, fabricated using TSMC's 0.18-μm SiGe Bi-CMOS technology, offers a unique combination of MOS and HBT bipolar junction transistors (BJTs). The double-balanced mixer uses Marchand baluns on the RF and LO ports to convert single-ended signals to differential ones. Transformer coupling between the RF transconductance and LO switching stages ensures excellent isolation and linearity. The proposed series-parallel switching stage effectively increases the switching current at frequencies above 10 GHz and improves the conversion gain at low voltages. The measured results for the proposed mixer demonstrate a power conversion gain of 3.4–4.7 dB with a flat variation of ±0.7 dB and an input third-order intercept point (IIP3) ranging from −1.8 to 0 dBm. These results indicate the performance of the mixer in terms of power gain and linearity. The isolation of RF-to-LO, RF-to-IF, and LO-to-IF are 60, 62, and 30 dB at 19 GHz, respectively, which is crucial for preventing signal interference. The total DC power consumption for 1.1/1 V dual voltage with output buffer is 16.6 mW. The total chip size is 1.11 × 0.843 mm<sup>2</sup>.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102358"},"PeriodicalIF":2.2,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comparative study of planar stacked integrated transformers for MMICs","authors":"Mokhtaria Derkaoui , Yamina Benhadda , Azzedine Hamid","doi":"10.1016/j.vlsi.2025.102346","DOIUrl":"10.1016/j.vlsi.2025.102346","url":null,"abstract":"<div><div>This paper describes the comparative study of different transformer topologies operating for Monolithic Microwave Integrated Circuit (MMIC). Planar stacked square, octagonal and circular coil topologies were studied to illustrate the good performance. The primary and secondary coils had the same dimensions with 1:1 turn ratio. The simplified physical equivalent circuit was demonstrated to evaluate its components values. Transformers prototype were fabricated using a standard 130 nm CMOS process. COMSOL Multiphysics analysis was carried out to show the electromagnetic and thermal behaviour. Simulations show quality factor improvements for the flipped circular topology. The square topology presents a high temperature and losses due to the right angles. The octagonal topology avoid to concentrates the current density in the angles but allows to increase the temperature due to the great number of segments. Measurements of insertion loss and coupling factor on circular topology demonstrate the good agreement with the proposed model. Simulated and measured magnitudes and phases for different outer diameter and width are identical. The results revealed that the planar transformer with the circular topology offers high performances.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102346"},"PeriodicalIF":2.2,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Ultra-low power linearized FVF based BD double diffusor double differential pair transconductor","authors":"Ravi Ranjan Kumar, Kulbhushan Sharma","doi":"10.1016/j.vlsi.2025.102345","DOIUrl":"10.1016/j.vlsi.2025.102345","url":null,"abstract":"<div><div>The demand for low-power transconductors capable of delivering linear performance is rising especially in biomedical applications. This work introduces a flipped voltage follower (FVF)-based bulk-driven (BD) double diffusor double differential pair (D<sup>4</sup>P) transconductor designed using 0.18 μm technology. The proposed design operates effectively at ±0.5 V, achieving a linear range of 0.2 V, transconductance (G<sub>m</sub>) of 1.07 μS, power dissipation of 0.365 μW, gain of 27 dB, a gain-bandwidth product of 27 kHz. Further analysis reveal the figure of merits, FOM<sub>1</sub> and FOM<sub>2</sub> values of proposed transconductor are 240 and 29.38, respectively with a linearity enhancement factor of 1.7 which are quite encouraging. Monte Carlo analysis show the G<sub>m</sub>, gain and total harmonic distortion have mean values of 1.06 μS, 26.13 dB, −47.40 dB, respectively which are close to their nominal values. The total layout area of the transconductor is 20204.54 μm<sup>2</sup>, providing a compact yet effective design for low-voltage applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102345"},"PeriodicalIF":2.2,"publicationDate":"2025-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A low-power two-step gray-code counter for single-slope ADC in CMOS image sensors","authors":"Xiaofeng Gu, Sikai Zhong, Xiaoyu Zhong, Taotao Zhou, Wenzhuo Li, Zhiguo Yu","doi":"10.1016/j.vlsi.2024.102341","DOIUrl":"10.1016/j.vlsi.2024.102341","url":null,"abstract":"<div><div>A low-power gray-code (GC) counter is proposed for the single-slope ADC (SS-ADC) in CMOS image sensors. The counter performs the GC counting directly to halve the clock frequency of each bit and minimize the flipping bits between two neighboring numbers. The bitwise-inversion (BWI) structure is utilized in the GC counter to perform complementary operations for the digital correlated double sampling. Moreover, a two-step (TS) GC counter with in-column error calibration is proposed to further reduce the power consumption. The TS-GC counter is implemented in a 10-bit SS-ADC. Simulated results show that the GC counter reduces power consumption by over 30% compared to a BWI counter, and the TS-GC counter reduces by over 18% compared to a TS double-data-rate counter. The differential nonlinearity and integral nonlinearity of the SS-ADC with the TS-GC counter are +0.4/<span><math><mo>−</mo></math></span>0.38 LSB and +0.45/<span><math><mo>−</mo></math></span>0.97 LSB, respectively, and the effective number of bits is 9.53 bit.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102341"},"PeriodicalIF":2.2,"publicationDate":"2025-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Thilagavathi , S. Senthil Kumar , D. Gowthami , A. Sridevi
{"title":"All pass transformation based variable digital filter design using low power approximate floating point adder and low power compressor based approximate multiplier","authors":"P. Thilagavathi , S. Senthil Kumar , D. Gowthami , A. Sridevi","doi":"10.1016/j.vlsi.2025.102344","DOIUrl":"10.1016/j.vlsi.2025.102344","url":null,"abstract":"<div><div>Digital signal processing filters are essential in various applications that require a balance between accuracy, power efficiency, and computational complexity. Variable digital filters (VDF) are increasingly important in signal processing and communication. This manuscript proposes All Pass Transformation dependent Variable Digital Filter using Low Power Approximate Floating Point Adder and Low Power Compressor based Approximate Multiplier (APT-VDF-LP-AFPA-LP-CAM). The proposed APT-VDF-LP-AFPA-LP-CAM overcomes performance limitations by utilizing advanced approximation techniques to enhance speed and reduce power consumption. The LP-AFPA leverages state-of-the-art approximate compound gates to accelerate addition and minimize carry propagation delays, while the LP-CAM employs a divide and conquer method for efficient partial product generation. The proposed approach is simulated using Xilinx ISE 14.5, shows significant improvements with 20.98 %, 12.67 % and 33.76 % reduction in delay and 21.90 %, 31.45 % and 27.45 % decrease in power consumption, and an operating frequency of 210.87 MHz. These advancements outperform existing methods, such as APT-VDF utilizing ternary adder and multiplier (APT-VDF-TA-TM), All-pass digital filters with dual carry select adder (CDF-ESDCSA-TRAF), Power-efficient FIR filters with ESSA and VL-CSKA (ESSA-VL-CSKA). This work underscores the effectiveness of integrating advanced approximation techniques in APT-VDF design, paving the way for future developments in high-speed and low-power digital signal processing applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102344"},"PeriodicalIF":2.2,"publicationDate":"2025-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A dynamic S-box algorithm based on special supersingular elliptic curve","authors":"Muhammad Hussain , Zia Bashir , M.G. Abbas Malik","doi":"10.1016/j.vlsi.2024.102340","DOIUrl":"10.1016/j.vlsi.2024.102340","url":null,"abstract":"<div><div>Recent research on substitution boxes (S-boxes) has highlighted the need for improved security and efficiency in cryptographic algorithms. This article addresses the limitations of existing S-box generation methods based on elliptic curves (ECs), which often suffer from inadequate computational efficiency and security vulnerabilities. We present a novel S-box algorithm developed from a special singular EC that overcomes these limitations. The algorithm consists of two main components: first, identifying limitations, and second, mitigating these limitations and creating a secure S-box by introducing novel models within a special supersingular EC framework. The S-box is then generated as a complementary element. We conducted comprehensive metric evaluations to assess the efficacy of the newly devised S-box. The proposed S-box has a generation time of 0.00015 s and shows ideal values regarding NL, LAP, DAP, BIC, and SAC. Additionally, our proposed S-box does not have fixed points or singularities, maintains a linear structure, and has a comparable computational complexity of <span><math><mrow><mi>O</mi><mrow><mo>(</mo><msup><mrow><mi>p</mi></mrow><mrow><mn>2</mn></mrow></msup><mo>)</mo></mrow></mrow></math></span>. Therefore, our proposed work is suitable for real-world applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102340"},"PeriodicalIF":2.2,"publicationDate":"2025-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of self-recovering low-cost multiple-node-upset-tolerant latch","authors":"Hongchen Li , Xiaofeng Zhao , Jie Li","doi":"10.1016/j.vlsi.2024.102342","DOIUrl":"10.1016/j.vlsi.2024.102342","url":null,"abstract":"<div><div>The radiation effects induced by particles in the radiation environments are the serious threat to the normal operation of electronic devices, and the single event effect can lead to soft errors in latches and destroy the stored data. With the technology scaling down, the Multiple Node Upset (MNU) induced by single event charge sharing has become the emerging reliability challenge of radiation-hardened designs. The radiation performance of latches can be improved by adding enough redundant nodes through spatial redundancy technique, but the overhead is significant and unacceptable. Therefore, in this work a Low-Cost MNU-Tolerant (LCMT) latch is proposed. By adding two redundant nodes to form the feedback loops and combining with layout-level techniques, the proposed LCMT latch can self-recover from MNU. SPICE simulations and 3D TCAD mixed-mode simulations were carried out with 65 nm commercial technology model to verify the robustness of the proposed latch to MNU. Compared with some existing radiation-hardened latches, the proposed LCMT latch has comparable or higher Single Event Upset (SEU) tolerance, lowest delay, lower power consumption, lower Power Delay Product (PDP), and lower delay sensitivity to Process, Voltage, and Temperature (PVT) variations. Compared with the same type of MNU-tolerant latch designs, the proposed LCMT latch saves about 60 % area overhead and about 46 % PDP.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102342"},"PeriodicalIF":2.2,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Research on modeling and prediction method of conducted electromagnetic interference for electric vehicle on-board charging system","authors":"Kai Zhou, Xiandong Ding, Zhipeng Xu","doi":"10.1016/j.vlsi.2024.102339","DOIUrl":"10.1016/j.vlsi.2024.102339","url":null,"abstract":"<div><div>In this paper, the conducted electromagnetic interference (EMI) prediction of two-stage cascade vehicle charging system is studied. Based on the analysis of the influence of parasitic capacitance on the EMI generated by on silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) and its propagation path, a simplified SiC MOSFET model with only parasitic capacitance is proposed. This model is used to predict the EMI of the system. In order to accurately simulate the working characteristics of the vehicle charging system, and by using the computational simulation method, the model of other components is established, the related parasitic parameters are extracted, and the whole system simulation and prediction model is constructed. On the basis of simulation research, the experimental platform of vehicle charging system is built, and the EMI experiment is verified by referring to relevant standards. Compared with the complete model, the simplified model can improve the speed of EMI prediction.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102339"},"PeriodicalIF":2.2,"publicationDate":"2024-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Viet-Thanh Pham , Jesus M. Munoz-Pacheco , Andrei Velichko , Salah Mahmoud Boulaaras , Shaher Momani
{"title":"A compact structure for triple-memristor maps with a hyperplane of fixed points","authors":"Viet-Thanh Pham , Jesus M. Munoz-Pacheco , Andrei Velichko , Salah Mahmoud Boulaaras , Shaher Momani","doi":"10.1016/j.vlsi.2024.102334","DOIUrl":"10.1016/j.vlsi.2024.102334","url":null,"abstract":"<div><div>Memristor maps verified the universal usage of memristors in nonlinear maps. Although almost published works investigate chaotic maps constructing with only one memristor, maps including multiple memristors attract interest because of their flexible structures. By combining three memristors, we introduce a triple-memristor model, which is general and can be easily used to design different chaotic maps. The presence of a hyperplane of fixed points and absence of fixed point are special characteristics of such a model. For illustrating the application of such a model, a specific triple-memristor map, named TMM<span><math><msub><mrow></mrow><mrow><mn>1</mn></mrow></msub></math></span> map, has been studied through both theoretical and experimental discoveries. Results indicate the chaos of TMM<span><math><msub><mrow></mrow><mrow><mn>1</mn></mrow></msub></math></span> map and its feasibility. The positive results show the potential of building chaotic maps with multiple memristors.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102334"},"PeriodicalIF":2.2,"publicationDate":"2024-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}