Haodong Hu , Jie Peng , Guiqing Liu , Shihao Yu , Zhongjin Zhao , Yufei Zhang , Chenxi Zhang , Zhiwei Li , Haijun Liu , Hui Xu , Yinan Wang
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引用次数: 0
Abstract
As compute-in-memory (CIM) architecture emerge to overcome the Von Neumann bottleneck, the efficient simulation of its core one-transistor-one-resistor (1T1R) crossbar array becomes critical.
Due to the compact nonlinear voltage division, the simulation efficiency of existing methods is hard to meet the simulation speed requirement of CIM chip design. Therefore, a novel numerical algorithm called dichotomy voltage division method (DVDM) was proposed. DVDM leverages interval bisection to bypass derivative calculations, achieving over 30 % speedup than the netlist-based Hspice method and 103-fold acceleration than the Matlab symbolic calculation method for DC scanning simulation. Crucially, DVDM's efficiency does not compromise fidelity to established compact models, which maintains equivalent accuracy to these established methods. Furthermore, DVDM successfully simulates the multiply accumulate operations—a cornerstone of neural network inference—demonstrating its potential to bridge device-level modeling and system-level CIM chip design. By balancing computational efficiency with model fidelity, DVDM provides a novel tool for rapid exploration of next-generation CIM systems.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.