{"title":"Hardware efficient approximate sigmoid activation function for classifying features around zero","authors":"Shreya Venkatesh, R. Sindhu, V. Arunachalam","doi":"10.1016/j.vlsi.2025.102421","DOIUrl":null,"url":null,"abstract":"<div><div>The binary classification of features around zero in an RNN-LSTM network requires accurate sigmoid activation. The approximate sigmoid activation function is preferred to reduce the computational complexity and hardware resources. Therefore, an IMDB dataset is considered for the Python-based data analysis, the features are passed through the LSTM layer, the dense layer, and finally the sigmoid activation function for binary classification. From the analysis, an approximate 3-term, 8-segment Taylor series sigmoid (<span><math><mrow><mrow><msub><mi>σ</mi><mrow><mi>T</mi><mo>_</mo><mn>3</mn><mo>_</mo><mn>8</mn></mrow></msub><mrow><mo>(</mo><mi>x</mi><mo>)</mo></mrow></mrow><mo>)</mo></mrow></math></span> is proposed with an 11-bit customized floating-point (CFP) and provides sufficient accuracy. The <span><math><mrow><msub><mi>σ</mi><mrow><mi>T</mi><mo>_</mo><mn>3</mn><mo>_</mo><mn>8</mn></mrow></msub><mrow><mo>(</mo><mi>x</mi><mo>)</mo></mrow></mrow></math></span> is implemented with an efficient range select controller, data scheduler and area-efficient arithmetic processing unit (APU). The APU is implemented with a CFP multiplier (CFP-Mul) and Exponent-aware CFP adder (EACFP-Add). Therefore, the FPGA implementation uses fewer hardware resources (LUT, FF and DSP) and obtained 1658 <strong><em>μ</em></strong>m<sup>2</sup> and 0.3305 mW power at 500 MHz in TSMC 65 nm ASIC implementation. This proposed function <span><math><mrow><msub><mi>σ</mi><mrow><mi>T</mi><mo>_</mo><mn>3</mn><mo>_</mo><mn>8</mn></mrow></msub><mrow><mo>(</mo><mi>x</mi><mo>)</mo></mrow></mrow></math></span> is used in the LSTM cell and classification layer. With the IMDB and SMS spam detection datasets, it provides near-classification metrics compared to the exact <em>σ</em>(<em>x</em>).</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102421"},"PeriodicalIF":2.2000,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025000781","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
The binary classification of features around zero in an RNN-LSTM network requires accurate sigmoid activation. The approximate sigmoid activation function is preferred to reduce the computational complexity and hardware resources. Therefore, an IMDB dataset is considered for the Python-based data analysis, the features are passed through the LSTM layer, the dense layer, and finally the sigmoid activation function for binary classification. From the analysis, an approximate 3-term, 8-segment Taylor series sigmoid ( is proposed with an 11-bit customized floating-point (CFP) and provides sufficient accuracy. The is implemented with an efficient range select controller, data scheduler and area-efficient arithmetic processing unit (APU). The APU is implemented with a CFP multiplier (CFP-Mul) and Exponent-aware CFP adder (EACFP-Add). Therefore, the FPGA implementation uses fewer hardware resources (LUT, FF and DSP) and obtained 1658 μm2 and 0.3305 mW power at 500 MHz in TSMC 65 nm ASIC implementation. This proposed function is used in the LSTM cell and classification layer. With the IMDB and SMS spam detection datasets, it provides near-classification metrics compared to the exact σ(x).
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.