Integration-The Vlsi Journal最新文献

{"title":"Op-Amp sizing via behavioral constraint generation and Gm/ID sampling","authors":"Mingzhen Li,&nbsp;Xisheng Zhang,&nbsp;Guoyong Shi","doi":"10.1016/j.vlsi.2025.102503","DOIUrl":"10.1016/j.vlsi.2025.102503","url":null,"abstract":"<div><div>Operational amplifier (Op-Amp) sizing is a non-trivial design task, especially for multiple-stage architectures. Traditional approaches (including artificial intelligence methods) require a large amount of trials and SPICE simulations. In this paper, we present an automated and efficient framework that integrates behavioral-level evaluation with gm/ID sampling, enhanced by auto-generated sizing constraints derived from circuit recognition. These constraints capture key relationships between design variables and performance-critical nodes, enabling targeted sampling via a bias-aware constraint graph and sequential strategy. This significantly improves the efficiency of both gm/ID sampling and behavioral-level evaluation. Following the behavioral sizing, a novel SPICE-based refinement is performed, where the Adaptive Moment Estimation (ADAM) algorithm is employed to efficiently fine-tune device parameters. The proposed strategy is validated through the sizing of 18 published multi-stage Op-Amps. In all cases, the auto-generated constraints effectively enhance the sizing process, enabling rapid convergence to fully functional designs that meet the target specifications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102503"},"PeriodicalIF":2.5,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144924945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved Shimizu-Morioka system and its application in image encryption","authors":"Tao Wu,&nbsp;Baoxiang Du,&nbsp;Zhijun Chai","doi":"10.1016/j.vlsi.2025.102527","DOIUrl":"10.1016/j.vlsi.2025.102527","url":null,"abstract":"<div><div>This work presents a memristive Shimizu-Morioka system (MSMS) constructed by integrating a universal voltage-controlled memristor model into the Shimizu-Morioka system. The regulatory mechanisms of parameter variations on state transitions and dynamic characteristics are elucidated through theoretical analysis. The results demonstrate that the MSMS exhibits constant Lyapunov exponents with respect to the memristive parameter, enabling flexible amplitude modulation of chaotic signals. NIST tests confirm that the chaotic sequences generated by the MSMS meet cryptographic standards. Multisim circuit simulations verify the system's engineering feasibility. Furthermore, the chaotic sequences are successfully applied to a novel image encryption scheme, validated through security analyses including key sensitivity, statistical attack resistance, anti-cropping, anti-noise performance and anti-differential attacks. This study bridges chaos theory with practical cryptographic applications, offering a foundation for advancing chaos-based secure communication and encryption technologies.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102527"},"PeriodicalIF":2.5,"publicationDate":"2025-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144924937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A programmable delay chain for the source-synchronous interface","authors":"Jen-Chieh Liu,&nbsp;Jun-Yu Chen,&nbsp;Wen-Qi Liu","doi":"10.1016/j.vlsi.2025.102517","DOIUrl":"10.1016/j.vlsi.2025.102517","url":null,"abstract":"<div><div>This paper describes a 5 ps timing resolution programmable delay chain (PDC) comprising a coarse-tuning delay line (CT-DL) and fine-timing delay line (FT-DL) to enable the user to adjust the delay time. For the process, voltage and temperature variations (PVT variations), the digital delay-locked loop (Digital DLL), and the auto-calibration circuit ensure that the programmable delay time is constant. The CT-DL and FT-DL adjust the delay time with a 5 ps delay time interval, employing a MUX-based scheme and the MOS varactor to define the delay tuning range and timing resolution. The CT-DL's timing resolution is determined via the DLL's one delay cell, with the FT-DL using an auto-calibration circuit to maintain a constant timing resolution. Thus, the PDC achieves a programmable delay time under the PVT variations. The test chip was implemented in a 90 nm CMOS process and a maximum operating frequency of 1 GHz. The power consumption was less than 505 μW when the PDC input was 100 MHz and the delay time range was 1.5 ns with a resolution and average accuracy of 5 ps and ±0.29 LSB, respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102517"},"PeriodicalIF":2.5,"publicationDate":"2025-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144931946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An algorithmic approach to construct the library of universal logic gates beyond NAND and NOR","authors":"Aadarsh Ganesh Goenka ,&nbsp;Shyamali Mitra ,&nbsp;KC Santosh ,&nbsp;Mrinal K. Naskar ,&nbsp;Nibaran Das","doi":"10.1016/j.vlsi.2025.102514","DOIUrl":"10.1016/j.vlsi.2025.102514","url":null,"abstract":"<div><div>In literature, NAND and NOR gates are recognized as Universal gates due to their functional completeness. This research focuses on exploring a diverse library of binary universal gates beyond these, along with a systematic method for categorizing logic connectives. Our study reveals an exponential growth in the number of Universal Gates within logic systems as the number of input variables, denoted as <span><math><mi>N</mi></math></span>, increases. For instance, with <span><math><mrow><mi>N</mi><mo>=</mo><mn>3</mn></mrow></math></span>, there are 56 Universal gates. The ratio of Universal gates to the total number of Logic gates is approximately 0.25. Additionally, the inclusion of constants 0 and 1 results in an expanded pool of Universal Gates, adding 4 (for <span><math><mrow><mi>N</mi><mo>=</mo><mn>2</mn></mrow></math></span>) and 169 (for <span><math><mrow><mi>N</mi><mo>=</mo><mn>3</mn></mrow></math></span>) more. This article considers mathematical and logical underpinnings of universal logic gates, presenting a search method, which is designed to identify these gates through diverse pathways. Moreover, a streamlined approach using hexadecimal representation expedites gate identification.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102514"},"PeriodicalIF":2.5,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Incremental/decremental memristor utilizing solely a voltage controlled second-generation current conveyor","authors":"Predrag Petrović,&nbsp;Vladica Mijailović","doi":"10.1016/j.vlsi.2025.102528","DOIUrl":"10.1016/j.vlsi.2025.102528","url":null,"abstract":"<div><div>In this study, a grounded incremental/decremental charge-controlled memristor emulator (MRE) is proposed, utilizing a single Voltage-Controlled Current Conveyor (VCCCII) as the active element along with a grounded capacitor. The emulator supports both incremental and decremental configurations, which are achieved through the incorporation of a simple switch. The proposed memristor emulator exhibits pinched hysteresis loops over a broad frequency range, up to 150 MHz, as verified through simulations conducted using TSMC 180 nm technology and the LTspice software, and the layout occupies an area of 620.5 μm². Additionally, a non-volatility test confirms the device's capability to retain memory. Comprehensive analyses, including Monte Carlo simulations, and temperature variations have been performed to assess the robustness of the proposed design. The emulator demonstrates low power consumption, with an average dissipation of 2.12 μW. A comparative performance evaluation with existing memristor emulators has been conducted to highlight its advantages. To evaluate the memory retention capability of the proposed memristor, a non-volatility test is conducted for both incremental and decremental configurations. The proposed solution offers a variable switching mechanism—soft and hard—depending on the value of the frequency of the input current signal and the applied capacitance. Furthermore, as an application, the proposed memristor design is integrated into Chua's oscillator and an adaptive learning circuit to validate its feasibility for neuromorphic applications. Moreover, current-mode circuits, owing to their numerous advantages—including lower power consumption and reduced chip area—facilitate fabrication using standard CMOS technologies. Finally, an experimental study has been carried out using commercially available AD844 and LM13700 components, demonstrating the practical feasibility of the proposed MRE.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102528"},"PeriodicalIF":2.5,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144903290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A systematic review of machine learning-driven design space exploration in high-level synthesis","authors":"Esra Celik,&nbsp;Deniz Dal","doi":"10.1016/j.vlsi.2025.102513","DOIUrl":"10.1016/j.vlsi.2025.102513","url":null,"abstract":"<div><div>In today’s rapidly evolving technological landscape, digitization across all sectors has intensified the complexity of hardware design processes due to increasing demands in data processing, artificial intelligence integration, and performance requirements. Innovative technologies such as the Internet of Things (IoT), 5G networks, big data analytics, and cloud computing introduce multifaceted requirements related to performance, flexibility, adaptability, and energy efficiency. These advancements present significant challenges in digital system design, requiring sophisticated solutions beyond traditional approaches. Conventional design methodologies show limitations in addressing the growing complexity and the resource-intensive nature of the design process. High-Level Synthesis (HLS) has emerged as a critical technology to accelerate digital system design and to enable the hardware implementation of complex algorithms. HLS converts software-level algorithmic specifications into hardware implementations, offering substantial time and cost benefits. However, the increasing complexity of modern digital systems has revealed the limitations of traditional design space exploration (DSE) methods, particularly in optimizing diverse design parameters. Machine learning-based DSE approaches offer transformative solutions, delivering improved efficiency and optimization capabilities in HLS workflows. This study provides a comprehensive analysis of ML-driven DSE techniques in HLS, focusing on innovative approaches to hardware design optimization. It evaluates the impact of various machine learning paradigms — including supervised learning, deep learning, reinforcement learning, and transfer learning — on optimizing critical metrics such as performance, energy efficiency, and resource utilization. ML-based DSE methods demonstrate high accuracy and computational efficiency across vast, multidimensional design spaces, significantly reducing manual efforts through data-driven decision mechanisms. This facilitates rapid evaluation of design parameters and improves development efficiency. Furthermore, ML-driven predictive models accelerate design workflows while reducing computational overhead from synthesis and simulation, enabling accurate predictions for performance, resource use, and energy consumption. The study also explores ML-based DSE contributions in multi-objective optimization, memory and power efficiency, and hardware accelerator design, emphasizing the role of advanced techniques such as Graph Neural Networks (GNNs) in modeling parameter interactions within HLS workflows. The paper concludes with a thorough discussion of the advantages, existing limitations, and future directions of ML-based DSE methods in HLS, highlighting their potential to enhance HLS workflows and meet the evolving demands of high-performance digital system design.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102513"},"PeriodicalIF":2.5,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144895675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Gm tunable CMOS transconductors for simultaneous multi-sine bioimpedance spectroscopy","authors":"Israel Corbacho ,&nbsp;Pietro Monsurrò ,&nbsp;Francisco Romero-Galán ,&nbsp;Miguel Á. Domínguez ,&nbsp;Alessandro Trifiletti ,&nbsp;Juan M. Carrillo","doi":"10.1016/j.vlsi.2025.102523","DOIUrl":"10.1016/j.vlsi.2025.102523","url":null,"abstract":"<div><div>Bioimpedance spectroscopy allows determining the characteristics of a medium through its electrical response. In dynamic events, the approach based on sequential bioimpedance analyses at different frequencies is not appropriate due to its duration. Simultaneous multi-sine spectroscopy is a suitable alternative to obtain the bioimpedance spectrum in a fast way. The practical implementation of this technique requires the design of programmable filters, which include tunable transconductors, for the separation of the different frequency components of the response signal. Two circuit techniques to design a transconductor with tunable transconductance (<span><math><msub><mrow><mi>G</mi></mrow><mrow><mi>m</mi></mrow></msub></math></span>), are proposed. The originality of the solution relies on the subtraction of the <span><math><msub><mrow><mi>G</mi></mrow><mrow><mi>m</mi></mrow></msub></math></span> of two voltage-to-current sections, thus leading not only to a wide tuning range of the effective <span><math><msub><mrow><mi>G</mi></mrow><mrow><mi>m</mi></mrow></msub></math></span> but also to a low value of this circuit parameter. The transconductors were designed and fabricated in 180 nm CMOS technology to operate with 1.8 V. Measurements on 9 samples of the silicon prototypes show that mismatch prevents achieving the very low <span><math><msub><mrow><mi>G</mi></mrow><mrow><mi>m</mi></mrow></msub></math></span> obtained in simulations, even though the deviations are within the variation ranges determined by a Montecarlo analysis. The SF and DP solutions display mean values for the maximum/minimum <span><math><msub><mrow><mi>G</mi></mrow><mrow><mi>m</mi></mrow></msub></math></span> of 10.29 <span><math><mi>μ</mi></math></span>A/V/149.5 nA/V and 10.1 <span><math><mi>μ</mi></math></span>A/V/302.8 nA/V, respectively, which represent transconductance tuning ratios of 68.8<span><math><mo>×</mo></math></span> and 33.4<span><math><mo>×</mo></math></span>, also respectively. Other remarkable feature of this proposal is that the second-order transconductor-capacitor (<span><math><msub><mrow><mi>G</mi></mrow><mrow><mi>m</mi></mrow></msub></math></span>-<em>C</em>) bandpass filters (BPFs), designed for signals separation, incorporate multiple-output versions of the proposed transconductors, thus leading to a reduction of area occupation and power consumption. The BPFs were designed to have nominal values of the gain at the centre frequency and of the quality factor of 0 dB and 2.83, respectively, whereas the centre frequency can be programmed over approximately one decade.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102523"},"PeriodicalIF":2.5,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144895674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hardware efficient design and implementation of multiplierless FIR filters using Sparse PSO on FPGA and ASIC","authors":"Teena Soni ,&nbsp;A. Kumar ,&nbsp;Ila Sharma ,&nbsp;Manoj Kumar Panda","doi":"10.1016/j.vlsi.2025.102519","DOIUrl":"10.1016/j.vlsi.2025.102519","url":null,"abstract":"<div><div>Efficient design and implementation of the FIR filter is the requirement of most of the DSP subsystems. This article presents a sparse particle swarm optimization (SPSO)-based FIR filters. A comparative analysis of the design of FIR filter is performed using accelerated PSO, quantum PSO, hybrid firefly PSO, and hybrid gravitational search PSO. The proposed design method outperforms existing methods in the literature. This work also proposes two efficient architectures for FIR filter implementation: improved parallel distributed arithmetic with carry-save adder tree and radix-2<em>r</em> arithmetic with carry-save adder tree. The FPGA and ASIC implementation of the proposed architectures are performed. A 45 nm Nangate open cell library is used for ASIC implementation and a Basys 3 FPGA board is used for FPGA implementation. The hardware metrics such as resource utilization, power consumption, and delay are compared with existing architectures. The proposed parallel DA with CSA tree architecture provides 44.03 %, 54.91 %, and 77.33 % average reduction in slice LUTs, slices utilization, and power consumption, respectively, and the proposed radix-2<em>r</em> FIR with CSA tree architecture provides an average reduction of 47.11 % in slice LUTs and 56.37 % slices utilization for FPGA implementation. For ASIC implementation, the average reduction of 71.74 % in area and 67.27 % in area-power product (APP) using the proposed parallel DA with CSA tree architecture is obtained. The proposed radix-2<em>r</em>-based FIR with CSA tree architecture provides an average reduction of 87.24 % in area, 59.74 % in area-delay product ADP, and 90.98 % in APP, compared with architectures in previous works.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102519"},"PeriodicalIF":2.5,"publicationDate":"2025-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144895673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A real-time integrated eye tracker with in-pixel image processing in 0.18-μm CMOS technology","authors":"Ahmad Mouri Zadeh Khaki,&nbsp;Ahyoung Choi","doi":"10.1016/j.vlsi.2025.102526","DOIUrl":"10.1016/j.vlsi.2025.102526","url":null,"abstract":"<div><div>This paper presents a high-speed eye tracker system (ETS) that leverages an in-pixel image processing array along with a fully parallel architecture to achieve real-time performance. The proposed ETS performs pixel-level image processing in digital domain using morphological operations—erosion and dilation—to determine the pupil and corneal glint centers essential for gaze tracking. Designed for seamless integration with conventional and custom CMOS image sensors (CISs), the system eliminates the need for external peripherals and storage circuits, significantly reducing power consumption and processing time compared to prior works. The 176 × 120 pixel array prototype of the proposed design was implemented in 0.18-μm CMOS technology. Post-layout simulations show a maximum tracking error of ±1 pixel and a processing time of 500 ns at 25 MHz. The system operates at 12.61 μW with a 1.8 V supply, demonstrating its suitability for real-time applications in human-computer interaction (HCI) and medical diagnostics.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102526"},"PeriodicalIF":2.5,"publicationDate":"2025-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144903291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA-based pipelined kNN accelerator with early termination optimization","authors":"Sandra Djosic,&nbsp;Milica Jovanovic,&nbsp;Goran Lj,Djordjevic","doi":"10.1016/j.vlsi.2025.102515","DOIUrl":"10.1016/j.vlsi.2025.102515","url":null,"abstract":"<div><div>In this paper, we present the design and implementation of a high-throughput pipelined k-Nearest Neighbors (kNN) hardware accelerator optimized for System-on-Chip (SoC) FPGA platforms. To address the computational intensity of extensive distance calculations in kNN, we propose a novel approach that combines algorithmic and architectural optimizations. Central to our design is an early termination mechanism that reduces redundant computations by halting distance evaluations exceeding the current kNN radius. We enhance the baseline early termination strategy by incorporating techniques for estimating initial distances and optimizing iterative computations for both Manhattan and Euclidean distance metrics. These algorithmic improvements are supported by a pipelined hardware architecture featuring checkpoint-based early termination, drip-feeding mechanisms, and configurable pipeline stages. Additionally, we develop a custom software tool that enables design space exploration, allowing fine-tuned configuration of architectural parameters for optimal performance and resource efficiency across diverse datasets. The proposed design is implemented and evaluated on an AMD Zynq-7010 SoC FPGA platform. Experimental results demonstrate significant throughput improvements, delivering up to a 4x speedup over the baseline brute-force kNN pipeline architecture, while maintaining low resource utilization. These results highlight the effectiveness of our kNN accelerator for embedded applications requiring high throughput machine learning capabilities.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102515"},"PeriodicalIF":2.5,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144893249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}