{"title":"增量/递减忆阻器仅利用电压控制的第二代电流输送器","authors":"Predrag Petrović, Vladica Mijailović","doi":"10.1016/j.vlsi.2025.102528","DOIUrl":null,"url":null,"abstract":"<div><div>In this study, a grounded incremental/decremental charge-controlled memristor emulator (MRE) is proposed, utilizing a single Voltage-Controlled Current Conveyor (VCCCII) as the active element along with a grounded capacitor. The emulator supports both incremental and decremental configurations, which are achieved through the incorporation of a simple switch. The proposed memristor emulator exhibits pinched hysteresis loops over a broad frequency range, up to 150 MHz, as verified through simulations conducted using TSMC 180 nm technology and the LTspice software, and the layout occupies an area of 620.5 μm<sup>2</sup>. Additionally, a non-volatility test confirms the device's capability to retain memory. Comprehensive analyses, including Monte Carlo simulations, and temperature variations have been performed to assess the robustness of the proposed design. The emulator demonstrates low power consumption, with an average dissipation of 2.12 μW. A comparative performance evaluation with existing memristor emulators has been conducted to highlight its advantages. To evaluate the memory retention capability of the proposed memristor, a non-volatility test is conducted for both incremental and decremental configurations. The proposed solution offers a variable switching mechanism—soft and hard—depending on the value of the frequency of the input current signal and the applied capacitance. Furthermore, as an application, the proposed memristor design is integrated into Chua's oscillator and an adaptive learning circuit to validate its feasibility for neuromorphic applications. Moreover, current-mode circuits, owing to their numerous advantages—including lower power consumption and reduced chip area—facilitate fabrication using standard CMOS technologies. Finally, an experimental study has been carried out using commercially available AD844 and LM13700 components, demonstrating the practical feasibility of the proposed MRE.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102528"},"PeriodicalIF":2.5000,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Incremental/decremental memristor utilizing solely a voltage controlled second-generation current conveyor\",\"authors\":\"Predrag Petrović, Vladica Mijailović\",\"doi\":\"10.1016/j.vlsi.2025.102528\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>In this study, a grounded incremental/decremental charge-controlled memristor emulator (MRE) is proposed, utilizing a single Voltage-Controlled Current Conveyor (VCCCII) as the active element along with a grounded capacitor. The emulator supports both incremental and decremental configurations, which are achieved through the incorporation of a simple switch. The proposed memristor emulator exhibits pinched hysteresis loops over a broad frequency range, up to 150 MHz, as verified through simulations conducted using TSMC 180 nm technology and the LTspice software, and the layout occupies an area of 620.5 μm<sup>2</sup>. Additionally, a non-volatility test confirms the device's capability to retain memory. Comprehensive analyses, including Monte Carlo simulations, and temperature variations have been performed to assess the robustness of the proposed design. The emulator demonstrates low power consumption, with an average dissipation of 2.12 μW. A comparative performance evaluation with existing memristor emulators has been conducted to highlight its advantages. To evaluate the memory retention capability of the proposed memristor, a non-volatility test is conducted for both incremental and decremental configurations. The proposed solution offers a variable switching mechanism—soft and hard—depending on the value of the frequency of the input current signal and the applied capacitance. Furthermore, as an application, the proposed memristor design is integrated into Chua's oscillator and an adaptive learning circuit to validate its feasibility for neuromorphic applications. Moreover, current-mode circuits, owing to their numerous advantages—including lower power consumption and reduced chip area—facilitate fabrication using standard CMOS technologies. Finally, an experimental study has been carried out using commercially available AD844 and LM13700 components, demonstrating the practical feasibility of the proposed MRE.</div></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":\"105 \",\"pages\":\"Article 102528\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2025-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926025001853\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025001853","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Incremental/decremental memristor utilizing solely a voltage controlled second-generation current conveyor
In this study, a grounded incremental/decremental charge-controlled memristor emulator (MRE) is proposed, utilizing a single Voltage-Controlled Current Conveyor (VCCCII) as the active element along with a grounded capacitor. The emulator supports both incremental and decremental configurations, which are achieved through the incorporation of a simple switch. The proposed memristor emulator exhibits pinched hysteresis loops over a broad frequency range, up to 150 MHz, as verified through simulations conducted using TSMC 180 nm technology and the LTspice software, and the layout occupies an area of 620.5 μm2. Additionally, a non-volatility test confirms the device's capability to retain memory. Comprehensive analyses, including Monte Carlo simulations, and temperature variations have been performed to assess the robustness of the proposed design. The emulator demonstrates low power consumption, with an average dissipation of 2.12 μW. A comparative performance evaluation with existing memristor emulators has been conducted to highlight its advantages. To evaluate the memory retention capability of the proposed memristor, a non-volatility test is conducted for both incremental and decremental configurations. The proposed solution offers a variable switching mechanism—soft and hard—depending on the value of the frequency of the input current signal and the applied capacitance. Furthermore, as an application, the proposed memristor design is integrated into Chua's oscillator and an adaptive learning circuit to validate its feasibility for neuromorphic applications. Moreover, current-mode circuits, owing to their numerous advantages—including lower power consumption and reduced chip area—facilitate fabrication using standard CMOS technologies. Finally, an experimental study has been carried out using commercially available AD844 and LM13700 components, demonstrating the practical feasibility of the proposed MRE.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.