增量/递减忆阻器仅利用电压控制的第二代电流输送器

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Predrag Petrović, Vladica Mijailović
{"title":"增量/递减忆阻器仅利用电压控制的第二代电流输送器","authors":"Predrag Petrović,&nbsp;Vladica Mijailović","doi":"10.1016/j.vlsi.2025.102528","DOIUrl":null,"url":null,"abstract":"<div><div>In this study, a grounded incremental/decremental charge-controlled memristor emulator (MRE) is proposed, utilizing a single Voltage-Controlled Current Conveyor (VCCCII) as the active element along with a grounded capacitor. The emulator supports both incremental and decremental configurations, which are achieved through the incorporation of a simple switch. The proposed memristor emulator exhibits pinched hysteresis loops over a broad frequency range, up to 150 MHz, as verified through simulations conducted using TSMC 180 nm technology and the LTspice software, and the layout occupies an area of 620.5 μm<sup>2</sup>. Additionally, a non-volatility test confirms the device's capability to retain memory. Comprehensive analyses, including Monte Carlo simulations, and temperature variations have been performed to assess the robustness of the proposed design. The emulator demonstrates low power consumption, with an average dissipation of 2.12 μW. A comparative performance evaluation with existing memristor emulators has been conducted to highlight its advantages. To evaluate the memory retention capability of the proposed memristor, a non-volatility test is conducted for both incremental and decremental configurations. The proposed solution offers a variable switching mechanism—soft and hard—depending on the value of the frequency of the input current signal and the applied capacitance. Furthermore, as an application, the proposed memristor design is integrated into Chua's oscillator and an adaptive learning circuit to validate its feasibility for neuromorphic applications. Moreover, current-mode circuits, owing to their numerous advantages—including lower power consumption and reduced chip area—facilitate fabrication using standard CMOS technologies. Finally, an experimental study has been carried out using commercially available AD844 and LM13700 components, demonstrating the practical feasibility of the proposed MRE.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102528"},"PeriodicalIF":2.5000,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Incremental/decremental memristor utilizing solely a voltage controlled second-generation current conveyor\",\"authors\":\"Predrag Petrović,&nbsp;Vladica Mijailović\",\"doi\":\"10.1016/j.vlsi.2025.102528\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>In this study, a grounded incremental/decremental charge-controlled memristor emulator (MRE) is proposed, utilizing a single Voltage-Controlled Current Conveyor (VCCCII) as the active element along with a grounded capacitor. The emulator supports both incremental and decremental configurations, which are achieved through the incorporation of a simple switch. The proposed memristor emulator exhibits pinched hysteresis loops over a broad frequency range, up to 150 MHz, as verified through simulations conducted using TSMC 180 nm technology and the LTspice software, and the layout occupies an area of 620.5 μm<sup>2</sup>. Additionally, a non-volatility test confirms the device's capability to retain memory. Comprehensive analyses, including Monte Carlo simulations, and temperature variations have been performed to assess the robustness of the proposed design. The emulator demonstrates low power consumption, with an average dissipation of 2.12 μW. A comparative performance evaluation with existing memristor emulators has been conducted to highlight its advantages. To evaluate the memory retention capability of the proposed memristor, a non-volatility test is conducted for both incremental and decremental configurations. The proposed solution offers a variable switching mechanism—soft and hard—depending on the value of the frequency of the input current signal and the applied capacitance. Furthermore, as an application, the proposed memristor design is integrated into Chua's oscillator and an adaptive learning circuit to validate its feasibility for neuromorphic applications. Moreover, current-mode circuits, owing to their numerous advantages—including lower power consumption and reduced chip area—facilitate fabrication using standard CMOS technologies. Finally, an experimental study has been carried out using commercially available AD844 and LM13700 components, demonstrating the practical feasibility of the proposed MRE.</div></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":\"105 \",\"pages\":\"Article 102528\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2025-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926025001853\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025001853","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

摘要

在这项研究中,提出了一种接地的增量/递减电荷控制记忆电阻模拟器(MRE),利用单个压控电流输送机(VCCCII)作为有源元件以及接地电容器。仿真器支持增量和递减配置,这是通过合并一个简单的开关来实现的。采用台积电180nm技术和LTspice软件进行的仿真验证了所设计的忆阻器仿真器在宽频率范围内具有可达150mhz的缩窄磁滞环,其布局面积为620.5 μm2。此外,非易失性测试证实了该设备保留内存的能力。综合分析,包括蒙特卡罗模拟,和温度变化已经执行,以评估所提出的设计的鲁棒性。仿真器功耗低,平均功耗为2.12 μW。并与现有的忆阻器仿真器进行了性能比较,以突出其优点。为了评估所提出的忆阻器的记忆保留能力,对增量和递减配置进行了非易失性测试。所提出的解决方案提供了一种可变的开关机制-软开关和硬开关-取决于输入电流信号的频率值和施加的电容。此外,作为应用,所提出的忆阻器设计集成到蔡氏振荡器和自适应学习电路中,以验证其在神经形态应用中的可行性。此外,电流模式电路由于其众多优势,包括更低的功耗和更小的芯片面积,便于使用标准CMOS技术制造。最后,利用市售的AD844和LM13700器件进行了实验研究,验证了所提出的MRE的实际可行性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Incremental/decremental memristor utilizing solely a voltage controlled second-generation current conveyor
In this study, a grounded incremental/decremental charge-controlled memristor emulator (MRE) is proposed, utilizing a single Voltage-Controlled Current Conveyor (VCCCII) as the active element along with a grounded capacitor. The emulator supports both incremental and decremental configurations, which are achieved through the incorporation of a simple switch. The proposed memristor emulator exhibits pinched hysteresis loops over a broad frequency range, up to 150 MHz, as verified through simulations conducted using TSMC 180 nm technology and the LTspice software, and the layout occupies an area of 620.5 μm2. Additionally, a non-volatility test confirms the device's capability to retain memory. Comprehensive analyses, including Monte Carlo simulations, and temperature variations have been performed to assess the robustness of the proposed design. The emulator demonstrates low power consumption, with an average dissipation of 2.12 μW. A comparative performance evaluation with existing memristor emulators has been conducted to highlight its advantages. To evaluate the memory retention capability of the proposed memristor, a non-volatility test is conducted for both incremental and decremental configurations. The proposed solution offers a variable switching mechanism—soft and hard—depending on the value of the frequency of the input current signal and the applied capacitance. Furthermore, as an application, the proposed memristor design is integrated into Chua's oscillator and an adaptive learning circuit to validate its feasibility for neuromorphic applications. Moreover, current-mode circuits, owing to their numerous advantages—including lower power consumption and reduced chip area—facilitate fabrication using standard CMOS technologies. Finally, an experimental study has been carried out using commercially available AD844 and LM13700 components, demonstrating the practical feasibility of the proposed MRE.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信