An algorithmic approach to construct the library of universal logic gates beyond NAND and NOR

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2025-08-23 DOI:10.1016/j.vlsi.2025.102514

Aadarsh Ganesh Goenka , Shyamali Mitra , KC Santosh , Mrinal K. Naskar , Nibaran Das

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引用次数: 0

Abstract

In literature, NAND and NOR gates are recognized as Universal gates due to their functional completeness. This research focuses on exploring a diverse library of binary universal gates beyond these, along with a systematic method for categorizing logic connectives. Our study reveals an exponential growth in the number of Universal Gates within logic systems as the number of input variables, denoted as

N

, increases. For instance, with

N = 3

, there are 56 Universal gates. The ratio of Universal gates to the total number of Logic gates is approximately 0.25. Additionally, the inclusion of constants 0 and 1 results in an expanded pool of Universal Gates, adding 4 (for

N = 2

) and 169 (for

N = 3

) more. This article considers mathematical and logical underpinnings of universal logic gates, presenting a search method, which is designed to identify these gates through diverse pathways. Moreover, a streamlined approach using hexadecimal representation expedites gate identification.

查看原文本刊更多论文

一种超越NAND和NOR的通用逻辑门库的构建算法

在文献中，NAND门和NOR门因其功能完备而被认为是通用门。本研究的重点是探索二进制通用门的多样化库，以及对逻辑连接词进行分类的系统方法。我们的研究表明，随着输入变量（表示为N）的增加，逻辑系统内通用门的数量呈指数增长。例如，当N=3时，有56个通用门。通用门与逻辑门总数的比例约为0.25。此外，包含常数0和1会导致Universal Gates池的扩展，增加4（对于N=2）和169（对于N=3）。本文考虑了通用逻辑门的数学和逻辑基础，提出了一种搜索方法，该方法旨在通过不同的途径识别这些门。此外，使用十六进制表示的简化方法加快了门的识别。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.