A programmable delay chain for the source-synchronous interface

This paper describes a 5 ps timing resolution programmable delay chain (PDC) comprising a coarse-tuning delay line (CT-DL) and fine-timing delay line (FT-DL) to enable the user to adjust the delay time. For the process, voltage and temperature variations (PVT variations), the digital delay-locked loop (Digital DLL), and the auto-calibration circuit ensure that the programmable delay time is constant. The CT-DL and FT-DL adjust the delay time with a 5 ps delay time interval, employing a MUX-based scheme and the MOS varactor to define the delay tuning range and timing resolution. The CT-DL's timing resolution is determined via the DLL's one delay cell, with the FT-DL using an auto-calibration circuit to maintain a constant timing resolution. Thus, the PDC achieves a programmable delay time under the PVT variations. The test chip was implemented in a 90 nm CMOS process and a maximum operating frequency of 1 GHz. The power consumption was less than 505 μW when the PDC input was 100 MHz and the delay time range was 1.5 ns with a resolution and average accuracy of 5 ps and ±0.29 LSB, respectively.