A real-time integrated eye tracker with in-pixel image processing in 0.18-μm CMOS technology

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2025-08-22 DOI:10.1016/j.vlsi.2025.102526

Ahmad Mouri Zadeh Khaki, Ahyoung Choi

{"title":"A real-time integrated eye tracker with in-pixel image processing in 0.18-μm CMOS technology","authors":"Ahmad Mouri Zadeh Khaki, Ahyoung Choi","doi":"10.1016/j.vlsi.2025.102526","DOIUrl":null,"url":null,"abstract":"<div><div>This paper presents a high-speed eye tracker system (ETS) that leverages an in-pixel image processing array along with a fully parallel architecture to achieve real-time performance. The proposed ETS performs pixel-level image processing in digital domain using morphological operations—erosion and dilation—to determine the pupil and corneal glint centers essential for gaze tracking. Designed for seamless integration with conventional and custom CMOS image sensors (CISs), the system eliminates the need for external peripherals and storage circuits, significantly reducing power consumption and processing time compared to prior works. The 176 × 120 pixel array prototype of the proposed design was implemented in 0.18-μm CMOS technology. Post-layout simulations show a maximum tracking error of ±1 pixel and a processing time of 500 ns at 25 MHz. The system operates at 12.61 μW with a 1.8 V supply, demonstrating its suitability for real-time applications in human-computer interaction (HCI) and medical diagnostics.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102526"},"PeriodicalIF":2.5000,"publicationDate":"2025-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S016792602500183X","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

This paper presents a high-speed eye tracker system (ETS) that leverages an in-pixel image processing array along with a fully parallel architecture to achieve real-time performance. The proposed ETS performs pixel-level image processing in digital domain using morphological operations—erosion and dilation—to determine the pupil and corneal glint centers essential for gaze tracking. Designed for seamless integration with conventional and custom CMOS image sensors (CISs), the system eliminates the need for external peripherals and storage circuits, significantly reducing power consumption and processing time compared to prior works. The 176 × 120 pixel array prototype of the proposed design was implemented in 0.18-μm CMOS technology. Post-layout simulations show a maximum tracking error of ±1 pixel and a processing time of 500 ns at 25 MHz. The system operates at 12.61 μW with a 1.8 V supply, demonstrating its suitability for real-time applications in human-computer interaction (HCI) and medical diagnostics.

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基于0.18 μm CMOS技术的实时集成眼动仪

本文提出了一种高速眼动仪系统（ETS），该系统利用像素内图像处理阵列和全并行架构来实现实时性能。所提出的ETS在数字域使用形态学操作（侵蚀和扩张）进行像素级图像处理，以确定瞳孔和角膜闪烁中心，这是注视跟踪所必需的。该系统专为与传统和定制CMOS图像传感器（CISs）无缝集成而设计，无需外部外设和存储电路，与之前的工作相比，大大降低了功耗和处理时间。采用0.18 μm CMOS技术实现了176 × 120像素阵列原型。布局后仿真表明，在25 MHz下，最大跟踪误差为±1像素，处理时间为500 ns。该系统工作电压为12.61 μW，电源为1.8 V，适用于人机交互（HCI）和医疗诊断的实时应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.