Op-Amp sizing via behavioral constraint generation and Gm/ID sampling

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2025-08-29 DOI:10.1016/j.vlsi.2025.102503

Mingzhen Li, Xisheng Zhang, Guoyong Shi

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引用次数: 0

Abstract

Operational amplifier (Op-Amp) sizing is a non-trivial design task, especially for multiple-stage architectures. Traditional approaches (including artificial intelligence methods) require a large amount of trials and SPICE simulations. In this paper, we present an automated and efficient framework that integrates behavioral-level evaluation with gm/ID sampling, enhanced by auto-generated sizing constraints derived from circuit recognition. These constraints capture key relationships between design variables and performance-critical nodes, enabling targeted sampling via a bias-aware constraint graph and sequential strategy. This significantly improves the efficiency of both gm/ID sampling and behavioral-level evaluation. Following the behavioral sizing, a novel SPICE-based refinement is performed, where the Adaptive Moment Estimation (ADAM) algorithm is employed to efficiently fine-tune device parameters. The proposed strategy is validated through the sizing of 18 published multi-stage Op-Amps. In all cases, the auto-generated constraints effectively enhance the sizing process, enabling rapid convergence to fully functional designs that meet the target specifications.

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通过行为约束生成和Gm/ID抽样确定运放尺寸

运算放大器（Op-Amp）的尺寸是一项重要的设计任务，特别是对于多级架构。传统的方法（包括人工智能方法）需要大量的试验和SPICE模拟。在本文中，我们提出了一个自动化和高效的框架，该框架集成了行为级评估与gm/ID采样，并通过源自电路识别的自动生成尺寸约束进行了增强。这些约束捕获了设计变量和性能关键节点之间的关键关系，通过偏差感知约束图和顺序策略实现了目标采样。这大大提高了gm/ID取样和行为水平评估的效率。在行为调整之后，进行了一种新的基于spice的改进，其中采用自适应矩估计（ADAM）算法来有效地微调器件参数。通过18个已发布的多级运算放大器的尺寸验证了所提出的策略。在所有情况下，自动生成的约束有效地增强了尺寸确定过程，使快速收敛到满足目标规格的全功能设计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.