Hardware efficient design and implementation of multiplierless FIR filters using Sparse PSO on FPGA and ASIC

Abstract

Efficient design and implementation of the FIR filter is the requirement of most of the DSP subsystems. This article presents a sparse particle swarm optimization (SPSO)-based FIR filters. A comparative analysis of the design of FIR filter is performed using accelerated PSO, quantum PSO, hybrid firefly PSO, and hybrid gravitational search PSO. The proposed design method outperforms existing methods in the literature. This work also proposes two efficient architectures for FIR filter implementation: improved parallel distributed arithmetic with carry-save adder tree and radix-2r arithmetic with carry-save adder tree. The FPGA and ASIC implementation of the proposed architectures are performed. A 45 nm Nangate open cell library is used for ASIC implementation and a Basys 3 FPGA board is used for FPGA implementation. The hardware metrics such as resource utilization, power consumption, and delay are compared with existing architectures. The proposed parallel DA with CSA tree architecture provides 44.03 %, 54.91 %, and 77.33 % average reduction in slice LUTs, slices utilization, and power consumption, respectively, and the proposed radix-2r FIR with CSA tree architecture provides an average reduction of 47.11 % in slice LUTs and 56.37 % slices utilization for FPGA implementation. For ASIC implementation, the average reduction of 71.74 % in area and 67.27 % in area-power product (APP) using the proposed parallel DA with CSA tree architecture is obtained. The proposed radix-2r-based FIR with CSA tree architecture provides an average reduction of 87.24 % in area, 59.74 % in area-delay product ADP, and 90.98 % in APP, compared with architectures in previous works.