FPGA-based pipelined kNN accelerator with early termination optimization

In this paper, we present the design and implementation of a high-throughput pipelined k-Nearest Neighbors (kNN) hardware accelerator optimized for System-on-Chip (SoC) FPGA platforms. To address the computational intensity of extensive distance calculations in kNN, we propose a novel approach that combines algorithmic and architectural optimizations. Central to our design is an early termination mechanism that reduces redundant computations by halting distance evaluations exceeding the current kNN radius. We enhance the baseline early termination strategy by incorporating techniques for estimating initial distances and optimizing iterative computations for both Manhattan and Euclidean distance metrics. These algorithmic improvements are supported by a pipelined hardware architecture featuring checkpoint-based early termination, drip-feeding mechanisms, and configurable pipeline stages. Additionally, we develop a custom software tool that enables design space exploration, allowing fine-tuned configuration of architectural parameters for optimal performance and resource efficiency across diverse datasets. The proposed design is implemented and evaluated on an AMD Zynq-7010 SoC FPGA platform. Experimental results demonstrate significant throughput improvements, delivering up to a 4x speedup over the baseline brute-force kNN pipeline architecture, while maintaining low resource utilization. These results highlight the effectiveness of our kNN accelerator for embedded applications requiring high throughput machine learning capabilities.