An 8T SRAM cell for high-speed sub-threshold operation with dynamic body biasing

This paper presents a Transmission Gate based 8T SRAM cell with dynamic body biasing, featuring a SNM-free read port. The memory core uses 5 transistors (4 for cross-coupled inverters and 1 for feedback control). The design demonstrates consistent Hold Static Noise Margin (HSNM) and Read Static Noise Margin (RSNM) across 27^°C-75^°C, while the write margin (WM) increases linearly with temperature up to 75^°C before a slight decline. N-curve metrics—SVNM, SINM, WTV, and WTI—reveal stability trends: SVNM/SINM mirror HSNM/RSNM, WTV improves with temperature, and WTI degrades. Current parameters scale exponentially with supply voltage, whereas WTV and WM show linear voltage dependence. Power consumption remains stable across the tested temperature range but rises sharply with supply voltage. Write delay reduces significantly at higher voltages. The cell employs Dynamic Threshold MOS (DTMOS) logic, enhancing write speed (52 % faster than comparable designs) with an average write delay of 14.9 ns (7.35 ns for ‘0’). This speed improvement incurs higher power due to DTMOS-driven currents, with the write power being 4.3 times higher than the average of the other cells. The read power, however, is exactly equal to the average value of the other cells being at 1.47 nW, and static power is slightly higher than the average power of the other cells. The design provides stability in line with other cells tested, exceeding the immunity to current noise during read operations. The compact layout occupies 1.68 $\mu m^2$, smaller than several counterparts. The Design is optimized for speed while having stability and layout area in accordance with the average of the other cells, the power consumption of the cell is the attribute in which the design shows a strikingly inferior performance when compared to other cells.