Efficient high dimensional yield analysis for SRAM circuits via stack model and adaptive sampling

Abstract

Statistical yield analysis provides the relationship between performance and reliability in SRAM design at the expense of large simulation cost. In this paper, we developed a stack model based yield analysis method to minimize the simulation cost. In our stack model, a linear prior function is first modeled with sparse constraint to fit the overall trend and achieve feature selection. In order to ensure the accuracy near failure region, the modeling center will be shifted to the failure boundary by random-walk sampling. And the other two classical ensemble models will be constructed with the adaptive resampling strategy. Finally, a Machine Learning (ML) model is applied to best combine the predictions derived from these base models. When trained with small datasets generated from 28 nm memory circuits, our stack model shows competitive accuracy and efficiency compared with other state-of-art models.