High-performance radiation hardened latch using Schmitt trigger

Abstract

This paper presents a novel 45 nm CMOS radiation-hardened latch design for low-voltage applications. This paper focusses on the Schmitt trigger-based latch, which enhances robustness through increased node capacitance, providing better noise tolerance. While other types of latch designs uses redundant nodes for radiation hardening but faces reliability issues in modern technologies. This work presents two transient fault-tolerant latch designs based on a seven-transistor Schmitt trigger (STST). The proposed latch circuits are designed and implemented under the 45 nm CMOS technology node. The proposed latch provides the single event upset (SEU) tolerance using the STST latch to hold the correct state. The proposed designs for making STST latch radiation hardened is to increase the node capacitance at susceptible nodes by adding an STST block. The first design STST latch has a lower delay of 57%, a higher critical charge of 28.03%, a lower power of 43.86%, a lower power delay product (PDP) of 75.86%, and a higher critical charge to power delay area product ratio (QPAR) of 494.12% with a decreased area of 12.87% than recently proposed latches. The second design, the cascode seven-transistor Schmitt trigger (CSTST) latch, has a cascode feedback loop in place of a transmission gate and inverter with an improved critical charge of 11.74% and a higher critical charge to power delay area product ratio (QPAR) of 11.73% than the STST latch without an area increase.