高性能辐射硬化闩锁使用施密特触发器

IF 2.2 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Niraj Kumar , Chaudhary Indra Kumar , Neeta Pandey
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引用次数: 0

摘要

本文提出了一种新颖的45纳米CMOS抗辐射锁存器设计,用于低压应用。本文重点研究了基于Schmitt触发器的锁存器,该锁存器通过增加节点电容来增强鲁棒性,提供更好的噪声容忍度。而其他类型的闩锁设计采用冗余节点进行辐射硬化,但在现代技术中面临可靠性问题。这项工作提出了两种基于七晶体管施密特触发器(STST)的瞬态容错锁存设计。在45纳米CMOS技术节点下设计并实现了所提出的锁存电路。所提出的锁存器使用STST锁存器提供单事件干扰(SEU)容忍度来保持正确的状态。提出的强化STST锁存辐射的设计是通过增加STST块来增加敏感节点的节点电容。第一种设计的STST锁存器延迟低57%,临界电荷高28.03%,功率低43.86%,功率延迟积(PDP)低75.86%,临界电荷与功率延迟面积积比(QPAR)高494.12%,面积比最近提出的锁存器减少12.87%。第二种设计是级联七晶体管施密特触发器(CSTST)锁存器,用级联反馈回路代替传输门和逆变器,临界电荷提高到11.74%,临界电荷与功率延迟面积乘积比(QPAR)达到11.73%,而面积没有增加。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

High-performance radiation hardened latch using Schmitt trigger

High-performance radiation hardened latch using Schmitt trigger
This paper presents a novel 45 nm CMOS radiation-hardened latch design for low-voltage applications. This paper focusses on the Schmitt trigger-based latch, which enhances robustness through increased node capacitance, providing better noise tolerance. While other types of latch designs uses redundant nodes for radiation hardening but faces reliability issues in modern technologies. This work presents two transient fault-tolerant latch designs based on a seven-transistor Schmitt trigger (STST). The proposed latch circuits are designed and implemented under the 45 nm CMOS technology node. The proposed latch provides the single event upset (SEU) tolerance using the STST latch to hold the correct state. The proposed designs for making STST latch radiation hardened is to increase the node capacitance at susceptible nodes by adding an STST block. The first design STST latch has a lower delay of 57%, a higher critical charge of 28.03%, a lower power of 43.86%, a lower power delay product (PDP) of 75.86%, and a higher critical charge to power delay area product ratio (QPAR) of 494.12% with a decreased area of 12.87% than recently proposed latches. The second design, the cascode seven-transistor Schmitt trigger (CSTST) latch, has a cascode feedback loop in place of a transmission gate and inverter with an improved critical charge of 11.74% and a higher critical charge to power delay area product ratio (QPAR) of 11.73% than the STST latch without an area increase.
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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