Design and analysis of faithful parallel mean filter using approximate adders and 4:2 compressors for low-power VLSI architectures

Abstract

Area-efficient High-Speed processing filters are of utmost need for portable image and signal processing systems. Mean filter algorithms that perform simple arithmetic computing can be realized with less complex hardware. Approximate computing is a recent technique used to realize high-speed processing units for error-tolerant image and signal processing applications. In this article, we propose two fast Faithful Parallel Mean Filter (FPM) variants for digital image de-noising using novel approximate adders and 4:2 compressors. The proposed FPMs perform parallel accumulation on input pixels in a 3×3 kernel followed by a right-shift operation for reliable averaging to avoid overflow and maintain a fixed-width data path. The final output of the Average Estimation unit(AE) is used to replace the corrupted processing pixel(PP) in the 3×3 processing window. High-speed approximate adders, and 4:2 compressors that trade-off area at the expense of accuracy are proposed and implemented in the FPMs. The proposed faithful adders, 4:2 compressor-based accumulator units use hybrid logic that combines approximate computing in the least n/2 significant bits and exact addition in most n/2 significant bits. Approximation of least n/2 significant bits in the data-path units restricts the maximal error within a Unit Bit-Weight(UBW) at $2^{n/2}$. Parallel architectures for AE are proposed employing either adder or 4:2 compressors, and their performance is evaluated with new faithful adders and 4:2 compressor implementations. For an n×n processing window, adder variant AE(designated as AEadd) employs $(n^2-1)/2i$ adders, and 4:2 compressor variant AE(designated as $A{E}_{com}$), employ $(n^2-1)/4i$ compressors in each accumulation stage, where ‘i’ represents stage position. Synthesis with 90 nm ASIC technology revealed that to the least, the proposed FPM(using $A{E}_{add}$) demonstrates 31.5% Area-Delay Product(ADP), and 50% Power-Delay Product(PDP) reductions, compared to the standard FPM($FP{M}_{std}$). Implementations of the proposed $FP{M}_{add}$ and $FP{M}_{com}$ in digital image de-noising applications revealed superior Structural Similarity Index Measure (SSIM) of the processed outputs compared to the FPMs with state-of-the-art prior designs. Furthermore, a lower Mean Error Distance (MED) and Mean Relative Error Distance (MRED) of proposed FPM-based mean filters indicate minimal distortion in denoised images, preserving details and structure while effectively reducing noise, ensuring high-quality restoration and accuracy.