Low power current-mode hybrid computing architecture signal processing circuit

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Yuhang Lu, Huimin Liu
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引用次数: 0

Abstract

To address the increasingly prominent physical limitations and energy efficiency challenges in digital circuits, this paper proposes an innovative current-mode computing paradigm and presents a low-power current-mode hybrid computing architecture specifically designed for signal processing circuits. The core current-mode circuits of the architecture employ the MOSFET Translinear loop (MTL) principle. The key contributions include the structural simplification of the MTL nonlinear computing unit, flipped voltage follower biasing, which enables reliable low-voltage operation, and a significant reduction in silicon area and power consumption. The proposed design demonstrates versatile capabilities for implementing nonlinear functions, including square, absolute value, square root, and multiplication operations. By incorporating multiplier circuits, the design achieves a configurable-coefficient hybrid current-mode low-voltage discrete third-order Finite Impulse Response (FIR) filter, effectively mitigating the high-power consumption and area overhead caused by high-bit-width operations and fractional coefficients in conventional digital filter implementations. Additionally, a 6-bit flash current-mode ADC is introduced to serve as an interface between current-domain analog circuits and digital systems. Simulation results based on 28 nm CMOS technology with a 0.9V supply voltage confirm the functional robustness of the proposed circuit across temperature variations and process corners. Compared with conventional MTL implementations, the proposed solution not only achieves enhanced stability under low-voltage operation but also preserves computational accuracy comparable to 32-bit floating-point digital filters. Most notably, the hybrid architecture demonstrates significant improvements in both power efficiency (63 % reduction) and silicon area utilization (25 % reduction), setting a new state-of-the-art standard for energy-efficient signal processing systems.
低功耗电流模式混合计算架构信号处理电路
为了解决数字电路中日益突出的物理限制和能效挑战,本文提出了一种创新的电流模式计算范式,并提出了一种专为信号处理电路设计的低功耗电流模式混合计算架构。该架构的核心电流模式电路采用了MOSFET跨线性环路(MTL)原理。主要贡献包括MTL非线性计算单元的结构简化,翻转电压从动器偏置,实现可靠的低压运行,以及硅面积和功耗的显着减少。提出的设计展示了实现非线性函数的多种功能,包括平方,绝对值,平方根和乘法运算。通过结合乘法器电路,该设计实现了可配置系数混合电流模式低压离散三阶有限脉冲响应(FIR)滤波器,有效减轻了传统数字滤波器实现中由高位宽操作和分数系数引起的高功耗和面积开销。此外,还引入了一个6位闪存电流模式ADC,作为电流域模拟电路和数字系统之间的接口。基于28 nm CMOS技术、0.9V电源电压的仿真结果证实了该电路在温度变化和工艺拐角上的功能稳健性。与传统的MTL实现相比,该方案不仅提高了低压工作下的稳定性,而且保持了与32位浮点数字滤波器相当的计算精度。最值得注意的是,混合架构在功率效率(减少63%)和硅面积利用率(减少25%)方面都有显着改善,为节能信号处理系统设定了新的最先进标准。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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