{"title":"Low power current-mode hybrid computing architecture signal processing circuit","authors":"Yuhang Lu, Huimin Liu","doi":"10.1016/j.vlsi.2025.102571","DOIUrl":null,"url":null,"abstract":"<div><div>To address the increasingly prominent physical limitations and energy efficiency challenges in digital circuits, this paper proposes an innovative current-mode computing paradigm and presents a low-power current-mode hybrid computing architecture specifically designed for signal processing circuits. The core current-mode circuits of the architecture employ the MOSFET Translinear loop (MTL) principle. The key contributions include the structural simplification of the MTL nonlinear computing unit, flipped voltage follower biasing, which enables reliable low-voltage operation, and a significant reduction in silicon area and power consumption. The proposed design demonstrates versatile capabilities for implementing nonlinear functions, including square, absolute value, square root, and multiplication operations. By incorporating multiplier circuits, the design achieves a configurable-coefficient hybrid current-mode low-voltage discrete third-order Finite Impulse Response (FIR) filter, effectively mitigating the high-power consumption and area overhead caused by high-bit-width operations and fractional coefficients in conventional digital filter implementations. Additionally, a 6-bit flash current-mode ADC is introduced to serve as an interface between current-domain analog circuits and digital systems. Simulation results based on 28 nm CMOS technology with a 0.9V supply voltage confirm the functional robustness of the proposed circuit across temperature variations and process corners. Compared with conventional MTL implementations, the proposed solution not only achieves enhanced stability under low-voltage operation but also preserves computational accuracy comparable to 32-bit floating-point digital filters. Most notably, the hybrid architecture demonstrates significant improvements in both power efficiency (63 % reduction) and silicon area utilization (25 % reduction), setting a new state-of-the-art standard for energy-efficient signal processing systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102571"},"PeriodicalIF":2.5000,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025002287","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
To address the increasingly prominent physical limitations and energy efficiency challenges in digital circuits, this paper proposes an innovative current-mode computing paradigm and presents a low-power current-mode hybrid computing architecture specifically designed for signal processing circuits. The core current-mode circuits of the architecture employ the MOSFET Translinear loop (MTL) principle. The key contributions include the structural simplification of the MTL nonlinear computing unit, flipped voltage follower biasing, which enables reliable low-voltage operation, and a significant reduction in silicon area and power consumption. The proposed design demonstrates versatile capabilities for implementing nonlinear functions, including square, absolute value, square root, and multiplication operations. By incorporating multiplier circuits, the design achieves a configurable-coefficient hybrid current-mode low-voltage discrete third-order Finite Impulse Response (FIR) filter, effectively mitigating the high-power consumption and area overhead caused by high-bit-width operations and fractional coefficients in conventional digital filter implementations. Additionally, a 6-bit flash current-mode ADC is introduced to serve as an interface between current-domain analog circuits and digital systems. Simulation results based on 28 nm CMOS technology with a 0.9V supply voltage confirm the functional robustness of the proposed circuit across temperature variations and process corners. Compared with conventional MTL implementations, the proposed solution not only achieves enhanced stability under low-voltage operation but also preserves computational accuracy comparable to 32-bit floating-point digital filters. Most notably, the hybrid architecture demonstrates significant improvements in both power efficiency (63 % reduction) and silicon area utilization (25 % reduction), setting a new state-of-the-art standard for energy-efficient signal processing systems.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.