Integration-The Vlsi Journal最新文献_第2页

True random number generator design based on the fractional-order Sprott H chaotic system with statistical validation 基于分数阶Sprott H混沌系统的真随机数发生器设计及统计验证

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-24 DOI: 10.1016/j.vlsi.2025.102555

Mehmet Ziya Hoşbaş , Berkay Emi̇n , Akif Akgül , Fırat Kaçar

{"title":"True random number generator design based on the fractional-order Sprott H chaotic system with statistical validation","authors":"Mehmet Ziya Hoşbaş , Berkay Emi̇n , Akif Akgül , Fırat Kaçar","doi":"10.1016/j.vlsi.2025.102555","DOIUrl":"10.1016/j.vlsi.2025.102555","url":null,"abstract":"<div><div>The increasing demand for secure communication systems has emphasized the necessity of high-quality entropy sources in cryptographic applications. True Random Number Generators (TRNGs), which derive randomness from physical and chaotic processes, are essential for ensuring data confidentiality in domains such as the Internet of Things (IoT), healthcare, and wireless communication. This study presents a novel TRNG architecture based on the Fractional-Order Sprott H Chaotic System (FOSHCS), a model not previously employed in TRNG design. The chaotic properties of FOSHCS were rigorously evaluated through bifurcation diagrams, the maximum Lyapunov exponent (MLE), and attractor projections, confirming its viability as a reliable entropy source. The system was physically implemented on an NVIDIA Jetson AGX Orin platform using a custom-designed DAC circuit to observe the chaotic trajectories in the analog domain. Furthermore, real-time GPU temperature data was incorporated with the chaotic output to enhance entropy diversity. The resulting bitstreams underwent standard statistical randomness tests, including the NIST SP 800-22, FIPS 140-1, and ENT test suites, all of which were successfully passed. The integration of fractional-order chaotic modeling with physical entropy harvesting enabled the development of a compact and high-entropy TRNG suitable for embedded and security-critical applications. To the best of our knowledge, this work represents the first hardware realization of a TRNG based on the FOSHCS, offering a promising new direction in secure and robust random number generation.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102555"},"PeriodicalIF":2.5,"publicationDate":"2025-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145159453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fine-grained data integration for high throughput and bandwidth-efficient computation on FPGAs 在fpga上实现高吞吐量和带宽效率计算的细粒度数据集成

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-23 DOI: 10.1016/j.vlsi.2025.102563

Jiyuan Liu , Baoping Wang , Yongming Tang , He Li

引用次数: 0

An Adaptive Congestion-aware Approximate Communication (ACAC) scheme and implementation for Network-on-Chip systems 片上网络系统的自适应拥塞感知近似通信（ACAC）方案及其实现

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-20 DOI: 10.1016/j.vlsi.2025.102561

Shize Zhou , Wenjie Fan , Siyue Li , Yongqi Xue , Shiping Li , Songfeng Deng , Jinlun Ji , Tong Cheng , Xinyu Wang , Li Li , Yuxiang Fu

{"title":"An Adaptive Congestion-aware Approximate Communication (ACAC) scheme and implementation for Network-on-Chip systems","authors":"Shize Zhou , Wenjie Fan , Siyue Li , Yongqi Xue , Shiping Li , Songfeng Deng , Jinlun Ji , Tong Cheng , Xinyu Wang , Li Li , Yuxiang Fu","doi":"10.1016/j.vlsi.2025.102561","DOIUrl":"10.1016/j.vlsi.2025.102561","url":null,"abstract":"<div><div>Data-intensive applications like machine learning and pattern recognition impose heavy Network-on-Chip (NoC) communication loads, drastically increasing on-chip latency. Leveraging the error-tolerant nature of such applications, this paper proposes the Adaptive Congestion-Aware Approximate Communication (ACAC) scheme to dynamically balance approximation and reliability by detecting congestion distribution through three integrated strategies — source control (adjusting approximation rates at the source node), on-the-way control (refining decisions at intermediate routers), and a combined strategy. Cycle-accurate simulations shows a 6% to 36% saturated injection rate improvement over ABDTR under synthetic traffic and superior comprehensive performance across all strategies in real-application traces, particularly with the combined strategy achieving the best results while reducing additional control traffic by 52% compared to ABDTR. Despite these enhancements, the suggested framework incurs minimal hardware overhead, with only a 7.42% area increase and 7.79% power consumption rise relative to traditional NoC designs, demonstrating its potential as a scalable, application-aware solution for energy-efficient NoC optimization in error-resilient domains.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102561"},"PeriodicalIF":2.5,"publicationDate":"2025-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145121139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cross-channel image chain scrambling encryption algorithm using two memristor-based twin multi-scroll hyperchaotic systems 基于双忆阻器的双多涡旋超混沌系统的跨通道图像链置乱加密算法

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-19 DOI: 10.1016/j.vlsi.2025.102564

Zhenju Wang, Cong Wang, Ping Ma, Hongli Zhang, Shaohua Zhang

{"title":"Cross-channel image chain scrambling encryption algorithm using two memristor-based twin multi-scroll hyperchaotic systems","authors":"Zhenju Wang, Cong Wang, Ping Ma, Hongli Zhang, Shaohua Zhang","doi":"10.1016/j.vlsi.2025.102564","DOIUrl":"10.1016/j.vlsi.2025.102564","url":null,"abstract":"<div><div>This paper proposes a cross-channel image chain scrambling encryption algorithm based on two 5D memristive twin multi-scroll hyperchaotic systems. Firstly, two flux-controlled memristor models are introduced based on the simplification of Chua's system, and two 5D memristive twin multi-scroll hyperchaotic systems are designed by inputting different flux variables. The twin 5D memristive multi-scroll hyperchaotic systems exhibit the characteristics of variable scroll numbers and different topological structures. Secondly, a fractal-like cross-channel encryption algorithm is proposed, which combines cross-channel scrambling of sub-image and Zigzag transformation. Based on comprehensive experimental analysis, the results reveal that the key space is determined to be 2<sup>525</sup>, the information entropy of the ciphertext images across three channels approaches 7.9994, and the pixel correlation is reduced to nearly zero. Furthermore, NPCR and UACI exhibit values close to their theoretical benchmarks of 99.6094 % and 33.4635 %, respectively, highlighting the superior performance of the proposed encryption algorithm in terms of robustness and security.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102564"},"PeriodicalIF":2.5,"publicationDate":"2025-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145109850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MICSim: A modular pre-circuit simulator for mixed-signal compute-in-memory accelerators in CNNs and transformers MICSim：用于cnn和变压器中混合信号内存计算加速器的模块化预电路模拟器

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-18 DOI: 10.1016/j.vlsi.2025.102543

Cong Wang, Zeming Chen, Shanshi Huang

{"title":"MICSim: A modular pre-circuit simulator for mixed-signal compute-in-memory accelerators in CNNs and transformers","authors":"Cong Wang, Zeming Chen, Shanshi Huang","doi":"10.1016/j.vlsi.2025.102543","DOIUrl":"10.1016/j.vlsi.2025.102543","url":null,"abstract":"<div><div>This work introduces MICSim, an open-source, pre-circuit simulator designed to assist circuit designers to evaluate early-stage chip-level software performance and hardware overhead of mixed-signal compute-in-memory(CIM) accelerators. MICSim features a modular design, allowing easy multi-level co-design and design space exploration. Modularized from the state-of-the-art CIM simulator NeuroSim, MICSim provides a highly configurable simulation framework supporting multiple quantization algorithms, diverse circuit architecture designs, and different memory devices. This modular approach allows MICSim to be effectively extended to accommodate new designs.</div><div>MICSim natively enables evaluating accelerators’ software and hardware performance for convolutional neural networks (CNNs) and Transformers in Python, leveraging the popular PyTorch and Hugging Face Transformers frameworks. MICSim can be easily combined with optimization strategies to perform design space exploration and can be used for evaluating chip-level Transformers CIM accelerators, making it highly adaptable to different networks. Also, MICSim can achieve <span><math><mrow><mn>9</mn><mo>×</mo><mo>∼</mo><mn>32</mn><mo>×</mo></mrow></math></span> speedup of NeuroSim through a statistic-based average mode proposed by this work, without significant error across various networks. MICSim is available as an open-source tool on GitHub (<span><span>https:// github.com/ MICSim-official/MICSim_V1.0.git</span><svg><path></path></svg></span>).</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102543"},"PeriodicalIF":2.5,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145121140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A lossless floating capacitance multiplier based on the single DDCC− 一种基于单DDCC的无损浮动电容乘法器

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-17 DOI: 10.1016/j.vlsi.2025.102560

Tolga Yucehan , Erkan Yuce , Shahram Minaei , Costas Psychalinos

引用次数: 0

Online detection of hardware Trojan enabled packet tampering attack on network-on-chip: A Bayesian approach 基于贝叶斯方法的片上网络硬件木马数据包篡改攻击在线检测

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-17 DOI: 10.1016/j.vlsi.2025.102506

Xiaohang Wang , Ge Cao , Yiming Zhao , Yingtao Jiang , Amit Kumar Singh , Mei Yang , Liang Wang , Yinhe Han , Fen Guo

{"title":"Online detection of hardware Trojan enabled packet tampering attack on network-on-chip: A Bayesian approach","authors":"Xiaohang Wang , Ge Cao , Yiming Zhao , Yingtao Jiang , Amit Kumar Singh , Mei Yang , Liang Wang , Yinhe Han , Fen Guo","doi":"10.1016/j.vlsi.2025.102506","DOIUrl":"10.1016/j.vlsi.2025.102506","url":null,"abstract":"<div><div>Hardware Trojans (HTs), proven difficult to be detected and removed at the offline post-silicon stage, can secretly launch dangerous packet tampering attacks on the network-on-chip (NoC) of a many-core chip. In this paper, we present an online HT detection scheme that is based on continuous, on-the-fly assessment of how likely any single node in the NoC includes an HT. In specific, the scheme first collects the routing path information of any data packet flowing through the NoC. The probability of a node being infected with HTs will next be determined based on each packet’s authentication result and this probability is iteratively updated through Bayesian analysis. A node shall be marked as a high-risk node, if its probability of infection exceeds a threshold, and all the high-risk nodes thus discovered will be bypassed by any future traffic. Since the proposed scheme only needs end-to-end authentication, as opposed to costly hop-to-hop authentication, the hardware overhead is kept low. To help further reduce the bandwidth and computation overheads, three approximate schemes are also proposed. Experiments have confirmed that the proposed HT detection methods can effectively locate the malicious nodes and thus reduce the infection rate to below 5%.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102506"},"PeriodicalIF":2.5,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145097537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fredkin Gate-based Arbiter PUF design through challenge obfuscation using garbage outputs 基于Fredkin门的仲裁PUF设计，通过使用垃圾输出的挑战混淆

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-17 DOI: 10.1016/j.vlsi.2025.102531

Chinni Prabhunath G. , Ambika Prasad Shah

引用次数: 0

Weak signal detection and circuit implementation based on a novel 3D chaotic synchronization system 基于新型三维混沌同步系统的微弱信号检测与电路实现

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-17 DOI: 10.1016/j.vlsi.2025.102553

Shaohui Yan, Weitao Hu, Zihao Guo

{"title":"Weak signal detection and circuit implementation based on a novel 3D chaotic synchronization system","authors":"Shaohui Yan, Weitao Hu, Zihao Guo","doi":"10.1016/j.vlsi.2025.102553","DOIUrl":"10.1016/j.vlsi.2025.102553","url":null,"abstract":"<div><div>To address the performance limitations of traditional weak signal detection methods under low signal-to-noise ratio conditions and the challenges in hardware implementation of chaotic systems, this paper proposes a solution based on a three-dimensional dissipative chaotic system with a multi-equilibrium saddle-focus structure. The system’s complex dynamical behavior is revealed through phase diagrams, Lyapunov exponents spectra, and bifurcation diagram analysis. A nonlinear controller is designed using a drive-response synchronization control method to achieve rapid synchronization of the chaotic system within 0.1 s. Following the introduction of weak signals in a high-noise environment, their frequency is detected by analyzing the synchronization error. Modular circuit design and simulations are conducted, demonstrating that the system exhibits excellent detection performance and can realize frequency detection of weak signals over a wide frequency range. The hardware circuit is implemented using a four-layer FR-4 substrate process, offering advantages such as simple structure, high stability, and low complexity. The results demonstrate that the system efficiently detects weak signals’ frequency with a high signal-to-noise ratio (SNR) performance of -46.02 dB, highlighting its strong noise suppression capability and high detection sensitivity. This work lays a solid theoretical foundation for applications in engineering fields such as radar detection, mechanical fault diagnosis, and underwater signal processing, demonstrating significant potential for practical engineering application.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102553"},"PeriodicalIF":2.5,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145109851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An efficient architecture of truncated booth multiplier for AI application 一种适用于人工智能应用的截断展位乘法器的高效架构

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-16 DOI: 10.1016/j.vlsi.2025.102544

Shareefa Fairoose P. , Ashutosh Mishra

{"title":"An efficient architecture of truncated booth multiplier for AI application","authors":"Shareefa Fairoose P. , Ashutosh Mishra","doi":"10.1016/j.vlsi.2025.102544","DOIUrl":"10.1016/j.vlsi.2025.102544","url":null,"abstract":"<div><div>This paper presents truncated approximate booth multipliers (TR-ABMs) that are both energy- and area-efficient, leveraging novel Leading One/Zero Position Detectors (LOZPDs) and optimized approximate booth multiplier (ABM) architectures. The proposed <span>LOZPD</span>s enable substantial reductions in Area-Delay Product (<span>ADP</span>) and Power-Delay Product (<span>PDP</span>) relative to existing techniques. Two architectures are introduced: <span>TR-ABM1</span> integrates <span>LOZPD</span>-based operand truncation with a conventional Booth multiplier, while <span>TR-ABM2</span> employs an approximate Booth multiplier variant for further efficiency gains. The level of approximation is tunable through key design parameters, including multiplier width (<span><math><mi>w</mi></math></span>) and the number of partial product columns utilizing Approximate Partial Product Generators (<span>APG</span>s) and Approximate Compressors (<span>AC</span>s). Comprehensive error analysis is conducted via Monte Carlo simulations with 10 million random inputs, and the designs are synthesized using Cadence® Genus in 90 nm CMOS technology. The <span>TR-ABM</span>s are evaluated in neural network (<span>NN</span>) inference and 64-point Fast Fourier Transform (<span>FFT64</span>) applications. For MNIST handwritten digit classification, the <span>TR-ABM</span>s achieve accuracy on par with exact fixed-point Booth multipliers. In <span>FFT64</span>, the proposed designs deliver significant area and power savings over state-of-the-art approximate multipliers. Specifically, the <span>TR-ABM</span>s achieve 66.58%–75.59% reductions in <span>ADP</span> and 47.91%–60.94% reductions in <span>PDP</span>, while maintaining reliable computational accuracy. Overall, the <span>TR-ABM</span>s offer a superior accuracy-performance trade-off compared to prior approximate multipliers, making them highly suitable for energy-efficient artificial intelligence and signal processing applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102544"},"PeriodicalIF":2.5,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145097538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0