Integration-The Vlsi Journal最新文献_第2页

A broadband low-noise VCO circuit based on a hybrid analog-digital control loop

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-27 DOI: 10.1016/j.vlsi.2025.102374

Lixia Zheng, Yuxiao Li, Zilu Zhao, Hehe Tian, Jin Wu, Weifeng Sun

引用次数: 0

High-speed serial interface equalization tuning using metaheuristics

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-25 DOI: 10.1016/j.vlsi.2025.102369

Adán Torralba-Ayance, Astrid Maritza González-Zapata, Alejandro Díaz-Sánchez

引用次数: 0

Third-order resonance networks and their application to chaos generation

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-25 DOI: 10.1016/j.vlsi.2025.102348

Ahmed S. Elwakil , Brent J. Maundy , Costas Psychalinos , Amr Elsonbaty

引用次数: 0

A simulation optimization method for Verilog-AMS IBIS model under overclocking

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-24 DOI: 10.1016/j.vlsi.2025.102364

Yafei Ning , Zirui Zhang , Yuan Dong , Ziqi Zhang , Yuhan Xia

{"title":"A simulation optimization method for Verilog-AMS IBIS model under overclocking","authors":"Yafei Ning , Zirui Zhang , Yuan Dong , Ziqi Zhang , Yuhan Xia","doi":"10.1016/j.vlsi.2025.102364","DOIUrl":"10.1016/j.vlsi.2025.102364","url":null,"abstract":"<div><div>The Input/Output Buffer Information Specification (IBIS) model has effectively described the electrical characteristics of circuit input and output ports while safeguarding intellectual property. This model focuses on the analysis of the analog behavior of digital integrated circuits, specifically focusing on the electrical characteristic of I/O buffers, by considering the voltage and current waveforms of the digital I/O signals. However, under overclocking conditions, the model experiences distortion and reduced accuracy due to decreased circuit stability. To address this limitation, we introduce an optimized model designed to resist simulation distortions in the IBIS model during overclocking. First, we defined the relevant variables based on the IBIS circuit and constructed a physical model framework. Next, we studied the monotonicity and sufficient conditions of the physical model, established the relationship between model output and variable parameters, and derived the corresponding IBIS mathematical relationship. Then, to address distortion under overclocking conditions, we adjusted the model variables by setting weighting coefficients tailored to different scenarios, ensuring the output values were closer to the baseline model and significantly enhancing the model's resilience against overclocking distortions. Extensive optimization experiments on three different devices confirm the general applicability of our proposed method, achieving optimization rates exceeding 90 % while maintaining high consistency with the TL baseline model. Notably, our approach improves overclocking simulation accuracy by 21.7 % with only a 2.2 % increase in CPU time, surpassing existing methods. This work addresses the IBIS model's overclocking distortion issue, significantly advancing the accuracy of circuit device simulations.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102364"},"PeriodicalIF":2.2,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An on-chip temperature sensor with 0.5 °C resolution and 0.34% linearity error using 180-nm CMOS process

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-24 DOI: 10.1016/j.vlsi.2025.102362

Chua-Chin Wang , Pradyumna Vellanki , Shih-Heng Luo , Ralph Gerard B. Sangalang

引用次数: 0

Dynamical behaviors of the simple chaotic system with coexisting attractors and its synchronous application

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-23 DOI: 10.1016/j.vlsi.2025.102368

Shaohui Yan, Rong Lu, Hanbing Zhang

{"title":"Dynamical behaviors of the simple chaotic system with coexisting attractors and its synchronous application","authors":"Shaohui Yan, Rong Lu, Hanbing Zhang","doi":"10.1016/j.vlsi.2025.102368","DOIUrl":"10.1016/j.vlsi.2025.102368","url":null,"abstract":"<div><div>A simple 3D dissipative chaotic system with coexisting attractors is constructed in this paper. The dynamical behavior of the system is analyzed using numerical simulations of phase space and bifurcation diagrams as the parameters and initial conditions are varied. The amplitude of the state variable can be flexibly controlled by introducing the offset boosting, providing a controllable capability for the system. By analyzing and comparing the complexity, the initial condition with higher complexity is selected and used for synchronization control. The system is then subjected to circuit implementation. Finally, the synchronization of chaotic systems is realized by two synchronization methods, namely backstepping synchronization and finite-time synchronization. And the merits and drawbacks of the two synchronization methods are briefly compared and summarized. In contrast, finite-time synchronization demonstrates good performance, achieving synchronization times of 0.61 s and 0.81 s under different initial conditions. Thus, a circuit simulation for finite-time synchronization is conducted, with results consistent with the numerical simulation outcomes.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102368"},"PeriodicalIF":2.2,"publicationDate":"2025-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143288289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

CDA-GC: An effective cache data allocation for garbage collection in flash-based solid-state drives

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-22 DOI: 10.1016/j.vlsi.2025.102359

Keyu Wang , Huailiang Tan , Zaihong He , Jinyou Li , Keqin Li

{"title":"CDA-GC: An effective cache data allocation for garbage collection in flash-based solid-state drives","authors":"Keyu Wang , Huailiang Tan , Zaihong He , Jinyou Li , Keqin Li","doi":"10.1016/j.vlsi.2025.102359","DOIUrl":"10.1016/j.vlsi.2025.102359","url":null,"abstract":"<div><div>In the research of solid-state drive (SSD) performance enhancement, constructing an efficient garbage collection (GC) mechanism is crucial for accelerating device operations and extending their service life, especially in large data processing applications like databases and file systems. Therefore, this paper conducts an in-depth study on the impact of cache management strategies on GC performance and proposes an innovative GC algorithm called Cache Data Allocation GC (CDA-GC). By optimizing data allocation and management within the cache, this algorithm reduces unnecessary data migration during the GC process, thereby improving data processing efficiency and reducing the impact of GC operations on device performance. The core of CDA-GC lies in its innovative cache data management strategy, which can significantly reduce the data migration demands during the GC process. This method not only improves the overall processing performance of SSDs but also reduces the adverse impact of GC activities on device performance by optimizing data access patterns. We implemented and validated the algorithm on the Cosmos+ OpenSSD platform and compared it with existing advanced SSD caching strategies in real-world scenarios. Experimental results show that in database and file system applications, the CDA-GC algorithm can effectively improve performance.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102359"},"PeriodicalIF":2.2,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 2.69-ppm/°C curvature-compensated BJT-based bandgap voltage reference

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-21 DOI: 10.1016/j.vlsi.2025.102361

Hamidreza Rashidian , Iman Soltani , Mohammad Maghsoudi

引用次数: 0

Fractional-Order PI/PD and PID Controllers in Power Electronics: The step-down converter case

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-21 DOI: 10.1016/j.vlsi.2025.102360

Allan G.S. Sánchez , F.J. Pérez-Pinal

引用次数: 0

Chaos-based approaches to data security: Analysis of incommensurate fractional-order Arneodo chaotic system and engineering application on a microcomputer

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-18 DOI: 10.1016/j.vlsi.2025.102355

Akif Akgül , Mustafa Yaz , Berkay Emi̇n

{"title":"Chaos-based approaches to data security: Analysis of incommensurate fractional-order Arneodo chaotic system and engineering application on a microcomputer","authors":"Akif Akgül , Mustafa Yaz , Berkay Emi̇n","doi":"10.1016/j.vlsi.2025.102355","DOIUrl":"10.1016/j.vlsi.2025.102355","url":null,"abstract":"<div><div>In this study, the Arneodo chaotic system was designed as an incommensurate fractional-order system, and the equilibrium points, time series, and phase portraits of the system were obtained, while the Lyapunov exponents were calculated. The incommensurate fractional-order system was modeled and simulated on the Nvidia Jetson AGX Orin, and its practical applications were realized with the designed electronic circuit. The chaotic equations were discretized via the Grünwald–Letnikov method, and a random number generator (RNG) based on an embedded system was implemented using the proposed algorithm. The RNG successfully met the criteria of international statistical evaluations, including NIST 800-22, FIPS 140-1, and ENT, thereby serving as a foundation for encryption and steganography algorithms. An original image encryption algorithm based on an embedded system was developed using the incommensurate fractional-order chaotic RNG. Encryption algorithm performance was evaluated through various security analyses, demonstrating the success of the incommensurate fractional-order Arneodo (IFOAR) system in embedded encryption applications. Furthermore, an embedded system-based image steganography algorithm was developed using the designed RNG, providing two-level security. The effectiveness of incommensurate chaotic system in steganography applications has been proved by various security analyses.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102355"},"PeriodicalIF":2.2,"publicationDate":"2025-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143288595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0