Integration-The Vlsi Journal最新文献

{"title":"Electronically tunable floating DXCCDITA-based universal memelement emulator and its applications","authors":"Shalini ,&nbsp;Kunwar Singh ,&nbsp;Shireesh Kumar Rai","doi":"10.1016/j.vlsi.2025.102476","DOIUrl":"10.1016/j.vlsi.2025.102476","url":null,"abstract":"<div><div>A universal memelement emulator is an electronic system that can emulate the behaviour of all three types of memelements (memristor, memcapacitor, and meminductor) with minor modifications to its arrangement. Despite significant technological advancements, the physical realization of memelements remains a challenging and unresolved problem, prompting ongoing research into innovative emulation techniques. This work presents a novel structure for a universal memelement emulator, which can be reconfigured into a desired memelement by manipulating the impedances within the proposed structure as either resistive or capacitive. The proposed circuit incorporates one dual X current conveyor differential input transconductance amplifier (DXCCDITA) and three passive components. The proposed structure can emulate a flux-controlled memristor, memcapacitor, and meminductor by appropriately choosing the impedances. The functionality of the proposed memelement emulator has been verified through simulations in LTspice utilizing TSMC 180 nm CMOS technology parameters. The proposed circuit shows satisfactory response up to 5 MHz frequency. Additionally, its functionality is verified using commercially available ICs. Furthermore, its practical utility is showcased by successful implementation in diverse applications, such as chaotic oscillator, high-pass filter, and adaptive learning circuit.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102476"},"PeriodicalIF":2.2,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144572683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and analysis of faithful parallel mean filter using approximate adders and 4:2 compressors for low-power VLSI architectures","authors":"K.N. Vijeyakumar ,&nbsp;Talluri Vineel Jessy ,&nbsp;K. Saranya ,&nbsp;B. Naresh Kumar Reddy","doi":"10.1016/j.vlsi.2025.102462","DOIUrl":"10.1016/j.vlsi.2025.102462","url":null,"abstract":"&lt;div&gt;&lt;div&gt;Area-efficient High-Speed processing filters are of utmost need for portable image and signal processing systems. Mean filter algorithms that perform simple arithmetic computing can be realized with less complex hardware. Approximate computing is a recent technique used to realize high-speed processing units for error-tolerant image and signal processing applications. In this article, we propose two fast Faithful Parallel Mean Filter (FPM) variants for digital image de-noising using novel approximate adders and 4:2 compressors. The proposed FPMs perform parallel accumulation on input pixels in a 3×3 kernel followed by a right-shift operation for reliable averaging to avoid overflow and maintain a fixed-width data path. The final output of the Average Estimation unit(AE) is used to replace the corrupted processing pixel(PP) in the 3×3 processing window. High-speed approximate adders, and 4:2 compressors that trade-off area at the expense of accuracy are proposed and implemented in the FPMs. The proposed faithful adders, 4:2 compressor-based accumulator units use hybrid logic that combines approximate computing in the least n/2 significant bits and exact addition in most n/2 significant bits. Approximation of least n/2 significant bits in the data-path units restricts the maximal error within a Unit Bit-Weight(UBW) at &lt;span&gt;&lt;math&gt;&lt;msup&gt;&lt;mrow&gt;&lt;mn&gt;2&lt;/mn&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mi&gt;n&lt;/mi&gt;&lt;mo&gt;/&lt;/mo&gt;&lt;mn&gt;2&lt;/mn&gt;&lt;/mrow&gt;&lt;/msup&gt;&lt;/math&gt;&lt;/span&gt;. Parallel architectures for AE are proposed employing either adder or 4:2 compressors, and their performance is evaluated with new faithful adders and 4:2 compressor implementations. For an n×n processing window, adder variant AE(designated as AEadd) employs &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mrow&gt;&lt;mo&gt;(&lt;/mo&gt;&lt;msup&gt;&lt;mrow&gt;&lt;mi&gt;n&lt;/mi&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mn&gt;2&lt;/mn&gt;&lt;/mrow&gt;&lt;/msup&gt;&lt;mo&gt;−&lt;/mo&gt;&lt;mn&gt;1&lt;/mn&gt;&lt;mo&gt;)&lt;/mo&gt;&lt;/mrow&gt;&lt;mo&gt;/&lt;/mo&gt;&lt;mn&gt;2&lt;/mn&gt;&lt;mi&gt;i&lt;/mi&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt; adders, and 4:2 compressor variant AE(designated as &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;A&lt;/mi&gt;&lt;msub&gt;&lt;mrow&gt;&lt;mi&gt;E&lt;/mi&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mi&gt;c&lt;/mi&gt;&lt;mi&gt;o&lt;/mi&gt;&lt;mi&gt;m&lt;/mi&gt;&lt;/mrow&gt;&lt;/msub&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;), employ &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mrow&gt;&lt;mo&gt;(&lt;/mo&gt;&lt;msup&gt;&lt;mrow&gt;&lt;mi&gt;n&lt;/mi&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mn&gt;2&lt;/mn&gt;&lt;/mrow&gt;&lt;/msup&gt;&lt;mo&gt;−&lt;/mo&gt;&lt;mn&gt;1&lt;/mn&gt;&lt;mo&gt;)&lt;/mo&gt;&lt;/mrow&gt;&lt;mo&gt;/&lt;/mo&gt;&lt;mn&gt;4&lt;/mn&gt;&lt;mi&gt;i&lt;/mi&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt; compressors in each accumulation stage, where ‘i’ represents stage position. Synthesis with 90 nm ASIC technology revealed that to the least, the proposed FPM(using &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;A&lt;/mi&gt;&lt;msub&gt;&lt;mrow&gt;&lt;mi&gt;E&lt;/mi&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mi&gt;a&lt;/mi&gt;&lt;mi&gt;d&lt;/mi&gt;&lt;mi&gt;d&lt;/mi&gt;&lt;/mrow&gt;&lt;/msub&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;) demonstrates 31.5% Area-Delay Product(ADP), and 50% Power-Delay Product(PDP) reductions, compared to the standard FPM(&lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;F&lt;/mi&gt;&lt;mi&gt;P&lt;/mi&gt;&lt;msub&gt;&lt;mrow&gt;&lt;mi&gt;M&lt;/mi&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mi&gt;s&lt;/mi&gt;&lt;mi&gt;t&lt;/mi&gt;&lt;mi&gt;d&lt;/mi&gt;&lt;/mrow&gt;&lt;/msub&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt;). Implementations of the proposed &lt;span&gt;&lt;math&gt;&lt;mrow&gt;&lt;mi&gt;F&lt;/mi&gt;&lt;mi&gt;P&lt;/mi&gt;&lt;msub&gt;&lt;mrow&gt;&lt;mi&gt;M&lt;/mi&gt;&lt;/mrow&gt;&lt;mrow&gt;&lt;mi&gt;a&lt;/mi&gt;&lt;mi&gt;d&lt;/mi&gt;&lt;mi&gt;d&lt;/mi&gt;&lt;/mrow&gt;&lt;/msub&gt;&lt;/mrow&gt;&lt;/math&gt;&lt;/span&gt; and &lt;spa","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102462"},"PeriodicalIF":2.2,"publicationDate":"2025-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144489497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A dual adaptive bias based low-dropout regulator with nonlinear current mirror loop for fast transient response","authors":"Yongqing Wang,&nbsp;Tianjun Sun,&nbsp;Jinhang Zhang,&nbsp;Qisheng Zhang","doi":"10.1016/j.vlsi.2025.102463","DOIUrl":"10.1016/j.vlsi.2025.102463","url":null,"abstract":"<div><div>Proposed in this study is a dual adaptive bias based low-dropout regulator (DAB-LDO) for wearable portable devices with fast transient response and superior control performance. Building on the conventional LDO with a single adaptive bias loop, we devise an additional adaptive bias nonlinear current mirror loop to provide a fast discharging slew rate at the gate of the power transistor. The proposed DAB-LDO regulator can achieve a better dynamic response including low undershoots and overshoots. Based on the proposed DAB-LDO, a simplified multi-loop analysis method is then developed to analyze the loop stability of the regulator. The DAB-LDO regulator is fabricated with the SMIC 180 nm process. It achieves a transient variation of 18 mV for 0- 50 mA of load step with an output capacitor of 1 <span><math><mi>μ</mi></math></span>F.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102463"},"PeriodicalIF":2.2,"publicationDate":"2025-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144489499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Semi-supervised lithography hotspot detection based on feature fusion and residual attention","authors":"Hui Xu ,&nbsp;Xinzhong Xiao ,&nbsp;Wenxin Huang ,&nbsp;Ruijun Ma ,&nbsp;Fuxin Tang ,&nbsp;Pan Qi ,&nbsp;Ye Yuan ,&nbsp;Huaguo Liang","doi":"10.1016/j.vlsi.2025.102472","DOIUrl":"10.1016/j.vlsi.2025.102472","url":null,"abstract":"<div><div>Given that traditional lithography hotspot detection methods based on semi-supervised learning struggle to meet the detection accuracy requirements of advanced integrated circuit (IC) manufacturing. To address the above challenges, a semi-supervised detection method based on feature fusion and residual attention is proposed in this paper. The method employs two inception modules as the multi-scale feature fusion module (MFF). These modules work in parallel to combine features from different layout scales. A residual attention module (RA) based on the convolutional block attention module (CBAM) is introduced, and a new neck network called RANeck is constructed using the RA module. The model utilizes the original layout features by constructing a joint multi-task network for classification and clustering through RANeck. The introduction of CBAM allows the model to focus more on important feature channels, thereby achieving more precise information filtering during feature processing. Additionally, a weighted cross-entropy loss function dynamically adjusts weights during the training process based on the number of lithography hotspots and nonhotspots, mitigating data imbalance effects and reducing false alarms. This method effectively leverages a large number of unlabeled data for training, improving the accuracy of lithography hotspot detection in the case of insufficient labeled data. The experimental results show that compared with the existing semi-supervised lithography hotspot detection methods, the proposed method has improved accuracy, false alarm, F1 score, and overall detection simulation time using 10 %–50 % of training data on the ICCAD 2012 contest benchmarks by 3.48 %, 22.03 %,12.76 %, and 20.26 %, respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102472"},"PeriodicalIF":2.2,"publicationDate":"2025-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144523351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reinforcement learning in integrated circuits: Design, synthesis, layout, and hardware security","authors":"Hakan Taşkıran ,&nbsp;Furkan Enes Hacımustafaoğlu ,&nbsp;Engin Afacan ,&nbsp;Günhan Dündar","doi":"10.1016/j.vlsi.2025.102460","DOIUrl":"10.1016/j.vlsi.2025.102460","url":null,"abstract":"<div><div>The growing complexity of semiconductor technology has led to an increased demand for advanced optimization and automation techniques in IC design. Among these, RL has emerged as a promising approach, offering the ability to explore vast design spaces and optimize performance metrics in ways traditional methods struggle to achieve. RL techniques have demonstrated their potential to complement and even outperform conventional methods in analog and RF IC design by autonomously learning optimal design strategies, from circuit synthesis and layout generation to performance optimization. Moreover, RL-based EDA tools have shown significant promise in addressing challenges related to process variation, power efficiency, and design security. In this context, recent progress in the utilization of RL for analog/RF circuit design is reviewed, with coverage of optimization, layout automation, and security, and emphasis placed on its pivotal role in advancing modern IC development.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102460"},"PeriodicalIF":2.2,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144489500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Robust optimization algorithm of RF MEMS switches considering uncertainties","authors":"Hao Yan ,&nbsp;Yaning Jia ,&nbsp;Chuangyuan Zeng ,&nbsp;Xiaoping Liao ,&nbsp;Xiao Shi","doi":"10.1016/j.vlsi.2025.102470","DOIUrl":"10.1016/j.vlsi.2025.102470","url":null,"abstract":"<div><div>Efficient robust design of RF MEMS switches requires balancing stringent performance criteria with inherent uncertainties. This paper proposes a Comprehensive Robust MEMS Optimization (CRMO) framework that integrates a Surrogate-assisted Differential Evolution with Screening Constraints (SDESC) and a Surrogate-assisted Multi-Objective Worst-case (SMOW) analysis method using both global and local regression models with particle swarm optimization (PSO). The SDESC algorithm adaptively adjusts constraint evaluations based on the proportion of feasible solutions, significantly reducing computational overhead, while SMOW efficiently handles multi-objective worst-case scenarios. Experimental evaluations on a 35 GHz series switch and an 10 GHz shunt switch demonstrate substantial performance and efficiency improvements. Specifically, for the series switch, the worst-case insertion loss improved from −6.742 dB to −0.134 dB, and the driving voltage was reduced from 58.345 V to 37.933 V; for the shunt switch, isolation was enhanced from −9.586 dB to −18.853 dB. Furthermore, the proposed algorithm achieves speedup from 3.2 × to 45 × over traditional PSO methods, confirming its advantage in both robustness and computational efficiency.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102470"},"PeriodicalIF":2.2,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144518292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An efficient XOR-free architecture for successive cancellation polar decoding","authors":"Navin Kumar ,&nbsp;Deepak Kedia ,&nbsp;Gaurav Purohit","doi":"10.1016/j.vlsi.2025.102467","DOIUrl":"10.1016/j.vlsi.2025.102467","url":null,"abstract":"<div><div>This paper presents a novel method for implementing an XOR-Free architecture for successive cancellation (SC) decoding in polar codes. From the hardware implementation perspective, the primary goal of this paper is to replace the XOR processing unit, which consumes significant dynamic power and processing time. The proposed architecture completely replaces the XOR operations of the SC polar decoder by using combinations of multiplexers and inverters. The proposed XOR-Free decoder retains the same functionality as that of traditional SC polar decoder. A comparative analysis of various SC polar decoders with the XOR-Free polar decoder is also presented. The proposed XOR-Free SC polar decoder is implemented with the Virtex Ultra-Scale FPGA family using AMD Xilinx Vivado. The implemented results reveal that the proposed architecture is more efficient in terms of hardware cost, power consumption, delay, and throughput.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102467"},"PeriodicalIF":2.2,"publicationDate":"2025-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144489498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A low power noise tolerant wide fan-in OR logic domino gate","authors":"Ankur Kumar ,&nbsp;Naman Garg ,&nbsp;R.K. Nagaria","doi":"10.1016/j.vlsi.2025.102468","DOIUrl":"10.1016/j.vlsi.2025.102468","url":null,"abstract":"<div><div>In this work, a low power noise tolerant domino gate is designed to reduce the leakage current and enhance the noise margin at optimized delay for wide fan-in OR logic. These improvements in the proposed domino gate have made in two phase. In the first phase, an arrangement, in which transmission gate along with static inverter, is designed to control the conduction of keeper transistor so that dynamic power and noise margin can be reduced and improved simultaneously. In second phase, two transistors having low threshold voltage in the evaluation network are inserted to decrease the subthreshold leakage current at optimized delay. Further, 256-bit wide multiplexer has been designed using the proposed domino gate to test the efficiency over the conventional domino. Thus, it is concluded that proposed domino is capable to design modern superscalar microprocessor, register file and other wide fan-in low power VLSI circuits. According to the simulation results, this work demonstrates a power consumption decrease of 20 % and 12 % as well as a noise margin improvement of 58 % and 25 % when compared with conventional domino and high speed domino, respectively. The cadence virtuoso EDA tool is used to evaluate and obtain the performance parameters of the designed gate along with existing work for 45 nm CMOS technology.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102468"},"PeriodicalIF":2.2,"publicationDate":"2025-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144548681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A machine learning-based design automation framework for differential mmWave LNAs","authors":"Anastasios Michailidis,&nbsp;Christos Sad,&nbsp;Thomas Noulis,&nbsp;Kostas Siozios","doi":"10.1016/j.vlsi.2025.102435","DOIUrl":"10.1016/j.vlsi.2025.102435","url":null,"abstract":"<div><div>In this work, a design methodology of a single-stage differential narrow-band mmWave LNA is presented using a novel full-design automation framework. A differential LNA test case vehicle was designed using a 22 nm FDSOI CMOS process and the ML framework was developed according to this specific process. The proposed framework is based on circuit optimization loops regarding noise figure, gain and impedance matching operating frequency. The proposed framework is capable of generating differential LNA designs with <span><math><mrow><mo>≥</mo><mn>99</mn><mtext>%</mtext></mrow></math></span> input/output matching efficiency, low noise <span><math><mrow><mo>&lt;</mo><mn>4</mn><mo>.</mo><mn>4</mn></mrow></math></span> dB, high gain <span><math><mrow><mo>&gt;</mo><mn>14</mn></mrow></math></span> dB, high linearity <span><math><mrow><mo>&gt;</mo><mo>−</mo><mn>19</mn></mrow></math></span> dBm, for frequencies of 32-91 GHz.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102435"},"PeriodicalIF":2.2,"publicationDate":"2025-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144471664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Innovative nonlinear component generator inspired by squirrel search algorithm","authors":"Fırat Artuğer","doi":"10.1016/j.vlsi.2025.102466","DOIUrl":"10.1016/j.vlsi.2025.102466","url":null,"abstract":"<div><div>The most used approach for data encryption is block cipher. One of the most important structures for block cipher algorithms is undoubtedly s-boxes. The s-box structure used in the AES algorithm contains 256 values. Therefore, obtaining powerful s-boxes is a rather difficult search problem. Because the search space is very large (256!). In this study, a new method based on squirrel search algorithm (SSA) is proposed to overcome this problem. The proposed method is displacement-based. In an s-box taken at the entrance, stronger s-box structures are sought by changing the location of the elements. The most important innovation in this study is that the elements to be displaced in the s-box were selected with the positioning states of the SSA. The chaotic Gompertz map was used for the initial population. Four different s-boxes were produced with the method developed thanks to the effective positioning states of SSA. As the fitness function, the nonlinearity value, which is the most important evaluation criterion of an s-box structure, was used. The proposed four s-box structures increased up to 110 nonlinearity values after only 4500 iterations. Here, it has been shown that the algorithm can be effective in all s-boxes by generating four different s-boxes. Considering these results, it has been determined that the proposed method gives more effective results than most methods in the literature.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102466"},"PeriodicalIF":2.2,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144480931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}