Integration-The Vlsi Journal最新文献_第2页

Dynamic precision configurable multiply and accumulate architecture for hardware accelerators 硬件加速器的动态精度可配置乘和累加结构

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-04-26 DOI: 10.1016/j.vlsi.2025.102419

Saraswathy B. , Anita Angeline A.

{"title":"Dynamic precision configurable multiply and accumulate architecture for hardware accelerators","authors":"Saraswathy B. , Anita Angeline A.","doi":"10.1016/j.vlsi.2025.102419","DOIUrl":"10.1016/j.vlsi.2025.102419","url":null,"abstract":"<div><div>The advantages of mixed precision over fixed precision deep neural network (DNN) accelerators in terms of efficiency with negligible accuracy loss have gained research interest in precision scalable DNN accelerators. Since most computations in DNN accelerators are multiply and accumulate (MAC), designing precision scalable MAC optimized in terms of area and power is crucial. The bottom-up approach of designing precision scalable MAC, achieving higher precision by shifting and adding the results of 2b <span><math><mo>×</mo></math></span> 2b multipliers, has become a wide-spread research interest due to its maximum utilization of available resources. It demands the efficient design of 2b <span><math><mo>×</mo></math></span> 2b multipliers and fusion units. This paper proposes four reduced computation bit brick units, customized to support a specific combination of signed/unsigned 2b <span><math><mo>×</mo></math></span> 2b multiplication, optimized for area and power. Then, an addition-optimized hybrid fusion unit with reduced computation bit bricks is proposed. To prove the superiority of the proposed design, the existing and proposed designs are modelled in Verilog, synthesized using 45 nm CMOS technology and compared. The results demonstrate a 32% reduction in area, 36% reduction in power and a 41% reduction in power delay product of the proposed design compared to the state-of-the-art designs.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102419"},"PeriodicalIF":2.2,"publicationDate":"2025-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143882265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Approximate subtractors designed for image processing applications 为图像处理应用设计的近似减法器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-04-25 DOI: 10.1016/j.vlsi.2025.102425

P. Divya Parameswari, A.V. Ananthalakshmi

引用次数: 0

A low-voltage and low-power PLL for Sub-GHz IoT applications 用于Sub-GHz物联网应用的低压低功率锁相环

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-04-24 DOI: 10.1016/j.vlsi.2025.102424

Jen-Chieh Liu, Rui-Cheng Ai

引用次数: 0

Orbital circuit elements table: A novel approach to elementary circuit elements 轨道电路元件表：基本电路元件的一种新方法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-04-14 DOI: 10.1016/j.vlsi.2025.102423

Omer Faruk Tozlu , Yunus Babacan , Firat Kacar

引用次数: 0

Image encryption/decryption accelerator based on Fast Cosine Number Transform 基于快速余弦数变换的图像加密/解密加速器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-04-12 DOI: 10.1016/j.vlsi.2025.102416

Zhiqiang Xu, Zhenmin Li, Feng Han, Xiaolei Wang, Gaoming Du

引用次数: 0

Design of new single-bit multilayer ALU in QCA technology QCA技术中新型单比特多层ALU的设计

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-04-11 DOI: 10.1016/j.vlsi.2025.102422

Reza Faraji, Abdalhossein Rezai

引用次数: 0

An efficient numerical simulation method based on practical 1T1R devices measurement for compute in memory chip design 一种基于实际1T1R器件测量的有效数值模拟方法，适用于存储芯片设计计算

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-04-11 DOI: 10.1016/j.vlsi.2025.102420

Haodong Hu , Jie Peng , Guiqing Liu , Shihao Yu , Zhongjin Zhao , Yufei Zhang , Chenxi Zhang , Zhiwei Li , Haijun Liu , Hui Xu , Yinan Wang

{"title":"An efficient numerical simulation method based on practical 1T1R devices measurement for compute in memory chip design","authors":"Haodong Hu , Jie Peng , Guiqing Liu , Shihao Yu , Zhongjin Zhao , Yufei Zhang , Chenxi Zhang , Zhiwei Li , Haijun Liu , Hui Xu , Yinan Wang","doi":"10.1016/j.vlsi.2025.102420","DOIUrl":"10.1016/j.vlsi.2025.102420","url":null,"abstract":"<div><div>As compute-in-memory (CIM) architecture emerge to overcome the Von Neumann bottleneck, the efficient simulation of its core one-transistor-one-resistor (1T1R) crossbar array becomes critical.</div><div>Due to the compact nonlinear voltage division, the simulation efficiency of existing methods is hard to meet the simulation speed requirement of CIM chip design. Therefore, a novel numerical algorithm called dichotomy voltage division method (DVDM) was proposed. DVDM leverages interval bisection to bypass derivative calculations, achieving over 30 % speedup than the netlist-based Hspice method and 10<sup>3</sup>-fold acceleration than the Matlab symbolic calculation method for DC scanning simulation. Crucially, DVDM's efficiency does not compromise fidelity to established compact models, which maintains equivalent accuracy to these established methods. Furthermore, DVDM successfully simulates the multiply accumulate operations—a cornerstone of neural network inference—demonstrating its potential to bridge device-level modeling and system-level CIM chip design. By balancing computational efficiency with model fidelity, DVDM provides a novel tool for rapid exploration of next-generation CIM systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102420"},"PeriodicalIF":2.2,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143860149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware efficient approximate sigmoid activation function for classifying features around zero 硬件高效近似s型激活函数对零附近特征进行分类

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-04-11 DOI: 10.1016/j.vlsi.2025.102421

Shreya Venkatesh, R. Sindhu, V. Arunachalam

{"title":"Hardware efficient approximate sigmoid activation function for classifying features around zero","authors":"Shreya Venkatesh, R. Sindhu, V. Arunachalam","doi":"10.1016/j.vlsi.2025.102421","DOIUrl":"10.1016/j.vlsi.2025.102421","url":null,"abstract":"<div><div>The binary classification of features around zero in an RNN-LSTM network requires accurate sigmoid activation. The approximate sigmoid activation function is preferred to reduce the computational complexity and hardware resources. Therefore, an IMDB dataset is considered for the Python-based data analysis, the features are passed through the LSTM layer, the dense layer, and finally the sigmoid activation function for binary classification. From the analysis, an approximate 3-term, 8-segment Taylor series sigmoid (<span><math><mrow><mrow><msub><mi>σ</mi><mrow><mi>T</mi><mo>_</mo><mn>3</mn><mo>_</mo><mn>8</mn></mrow></msub><mrow><mo>(</mo><mi>x</mi><mo>)</mo></mrow></mrow><mo>)</mo></mrow></math></span> is proposed with an 11-bit customized floating-point (CFP) and provides sufficient accuracy. The <span><math><mrow><msub><mi>σ</mi><mrow><mi>T</mi><mo>_</mo><mn>3</mn><mo>_</mo><mn>8</mn></mrow></msub><mrow><mo>(</mo><mi>x</mi><mo>)</mo></mrow></mrow></math></span> is implemented with an efficient range select controller, data scheduler and area-efficient arithmetic processing unit (APU). The APU is implemented with a CFP multiplier (CFP-Mul) and Exponent-aware CFP adder (EACFP-Add). Therefore, the FPGA implementation uses fewer hardware resources (LUT, FF and DSP) and obtained 1658 <strong><em>μ</em></strong>m<sup>2</sup> and 0.3305 mW power at 500 MHz in TSMC 65 nm ASIC implementation. This proposed function <span><math><mrow><msub><mi>σ</mi><mrow><mi>T</mi><mo>_</mo><mn>3</mn><mo>_</mo><mn>8</mn></mrow></msub><mrow><mo>(</mo><mi>x</mi><mo>)</mo></mrow></mrow></math></span> is used in the LSTM cell and classification layer. With the IMDB and SMS spam detection datasets, it provides near-classification metrics compared to the exact <em>σ</em>(<em>x</em>).</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102421"},"PeriodicalIF":2.2,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143823230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of 1T2R ReRAM array for in memory element-wise multiplication with distributed and majority logics 基于分布式多数逻辑的1T2R内存单元乘法阵列设计

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-04-07 DOI: 10.1016/j.vlsi.2025.102418

Ancy Joy , Jinsa Kuruvilla

{"title":"Design of 1T2R ReRAM array for in memory element-wise multiplication with distributed and majority logics","authors":"Ancy Joy , Jinsa Kuruvilla","doi":"10.1016/j.vlsi.2025.102418","DOIUrl":"10.1016/j.vlsi.2025.102418","url":null,"abstract":"<div><div>Multiplication is regarded as an essential component for inner product computation in Digital Signal Processing (DSP) applications. The frequent data transfers between the CPU and memory cause delays in traditional computer systems. In-memory computation (IMC) lowers latency by processing data at the location of storage. Because of its unique properties, Resistive Random-Access Memory (ReRAM) is a state-of-the-art non-volatile memory technology with many potential applications in IMC. On the other hand, the Conventional One Transistor One Resistor (1T1R) ReRAM bit-cell has a high bit-error rate and slower sensing during Non-Volatile Memory (NVM) storage. This study considers an in-memory element-wise multiplication using a One Transistor two Resistor (1T2R) ReRAM array. The adder-shifter module is the fundamental building block of element-wise multiplication. The majority logic is implemented in the proposed design as a memory READ operation. Additionally, distributed logics utilize look-up tables and adder-shifters to calculate inner products rather than multipliers and adders. It also addresses the high latency and intricate design associated with the traditional multiply and accumulate (MAC) method of implementing element-wise multiplication. According to the simulated results, the 1T2R cell uses less power and has a shorter write delay than the traditional 2T2R cell. Moreover, the sensing margin of the 1T2R bit cell remains 1.2 times larger than that of the 1T1R cell. In addition, compared to 1T1R and 2T2R cell-based designs, the proposed 1T2R design achieves 7.21 % and 48.24 % energy savings in element wise multiplication operation.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102418"},"PeriodicalIF":2.2,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143815011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

3D-multiscroll chaotic attractors design, circuit implementation and application to medical image encryption 三维多涡旋混沌吸引子设计、电路实现及在医学图像加密中的应用

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-04-04 DOI: 10.1016/j.vlsi.2025.102417

Jie Zhang, Jiangang Zuo

{"title":"3D-multiscroll chaotic attractors design, circuit implementation and application to medical image encryption","authors":"Jie Zhang, Jiangang Zuo","doi":"10.1016/j.vlsi.2025.102417","DOIUrl":"10.1016/j.vlsi.2025.102417","url":null,"abstract":"<div><div>Compared to traditional chaotic attractors, multiscroll chaotic attractors (MSCAs) have broad application potential in fields such as dynamical system research and information processing. This paper introduces 1D-MSCAs, 2D-MSCAs, and 3D-MSCAs based on the Sprott-A system by incorporating piecewise linear functions. Through a dynamical analysis using equilibrium points, Lyapunov exponents, and bifurcation diagrams, it is found that the MSCAs have no equilibrium points and possess hidden attractors. The system exhibits a rich variety of dynamical behaviors, including reverse multiplicative cycle bifurcation, transient chaos, and bursting chaos, as the parameters vary. Additionally, the system demonstrates initial offset behavior in response to changes in initial conditions. The MSCAs are validated through an analog circuit implementation. Furthermore, a novel cryptosystem is designed by integrating 3D-MSCAs with RNA operations, and its security performance is evaluated in terms of key sensitivity, histogram analysis, correlation, and information entropy. The analysis results indicate that the proposed cryptosystem offers high-security performance, providing a promising solution for medical image encryption.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102417"},"PeriodicalIF":2.2,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143786121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0