Integration-The Vlsi Journal最新文献_第2页

Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance 新型混合 TFET-FinFET 12T SRAM 单元，可提高写入裕度和读取性能

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-10-10 DOI: 10.1016/j.vlsi.2024.102294

Seyed Arman Sabaghpour, Behzad Ebrahimi, Pooya Torkzadeh

{"title":"Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance","authors":"Seyed Arman Sabaghpour, Behzad Ebrahimi, Pooya Torkzadeh","doi":"10.1016/j.vlsi.2024.102294","DOIUrl":"10.1016/j.vlsi.2024.102294","url":null,"abstract":"<div><div>This work presents two innovative 12T cells combining tunnel field-effect transistor (TFET) and fin field-effect transistor (FinFET) technologies. These cells address reverse bias current issues by incorporating separate paths for reading data and write enhancement cut transistors, enhancing hold/read/write static noise margin (H/R/WSNM), reducing read time, and minimizing power consumption from TFET leakage. At 0.6 V, the first (second) SRAM cell shows a WSNM improvement over O_7T, 8T, CA_10T, 12T, and HF_10T cells by 152 % (93 %), 152 % (93 %), 157.7 % (97.5 %), 95 % (50 %), and 104 % (57 %), respectively. The leakage power of the first (second) 12T TFET SRAM cell is two (four) orders of magnitude lower than O_7T and 8T SRAM cells. These hybrid SRAM cells also exhibit faster read operations across <em>V</em><sub>DD</sub> voltage levels (0.3 V–1 V) and the first 12T cell demonstrates shorter write access times than 12T and CA_10T SRAM cells. These characteristics make the proposed cells particularly suitable for energy-efficient IoT devices and medical applications, where balancing power, area, performance, and data integrity is critical.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102294"},"PeriodicalIF":2.2,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142437845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection 基于时延神经网络和遗传算法特征选择的流水线 ADC 数字背景校准算法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-10-10 DOI: 10.1016/j.vlsi.2024.102295

Yongsheng Yin, Long Li, Jiashen Li, Yukun Song, Honghui Deng, Hongmei Chen, Luotian Wu, Muqi Li, Xu Meng

{"title":"Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection","authors":"Yongsheng Yin, Long Li, Jiashen Li, Yukun Song, Honghui Deng, Hongmei Chen, Luotian Wu, Muqi Li, Xu Meng","doi":"10.1016/j.vlsi.2024.102295","DOIUrl":"10.1016/j.vlsi.2024.102295","url":null,"abstract":"<div><div>This paper presents a novel background calibration method for pipelined analog-to-digital converters (ADCs) using a time-delay neural network (TDNN), which is optimized through genetic algorithm (GA) techniques. The proposed technique leverages TDNN to create enhanced feature sets, significantly improving the calibration of nonlinear errors exhibiting memory effects. It harnesses the GA's global optimization capabilities for feature selection, effectively reducing the feature dimension and consequently alleviating the NN's computational burden. A parallel pipeline architecture is devised for the calibration circuit, with its implementation realized on FPGA to facilitate forward inference processing. The inference circuit is synthesized using TSMC's 90 nm CMOS process, achieving a power consumption of 40.11 mW and an area of 0.45 mm<sup>2</sup>. Simulations based on MATLAB for a 14-bit Pipelined ADC demonstrate that the proposed calibration method significantly improves the SFDR from 59.77 dB to 165.52 dB, and ENOB from 8.79 bits to 19.23 bits, surpassing the target ADC's specifications. Moreover, the dimensionality of features is effectively reduced by up to 34 % without compromising the calibration performance.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102295"},"PeriodicalIF":2.2,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142432446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel architecture of high performance fully differential two stage RFC OTA designed using DFVF and hybrid cascode compensation techniques 采用 DFVF 和混合级联补偿技术设计的新型高性能全差分两级 RFC OTA 架构

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-10-10 DOI: 10.1016/j.vlsi.2024.102296

Annu Dabas , Shweta Kumari , Maneesha Gupta , Richa Yadav

{"title":"A novel architecture of high performance fully differential two stage RFC OTA designed using DFVF and hybrid cascode compensation techniques","authors":"Annu Dabas , Shweta Kumari , Maneesha Gupta , Richa Yadav","doi":"10.1016/j.vlsi.2024.102296","DOIUrl":"10.1016/j.vlsi.2024.102296","url":null,"abstract":"<div><div>In this work, a novel fully differential two stage class AB Recycling Folded Cascode Operational Transconductance Amplifier (RFC OTA) using Differential Flipped Voltage Follower (DFVF) has been proposed. The DFVF and Dynamic Threshold Metal Oxide Semiconductor (DTMOS) transistors have been used as differential input stage of the proposed RFC OTA. These techniques provide enhancement in gain and bandwidth of the proposed OTA. To further improve the performance of proposed circuit, positive feedback at current mirror load along with Hybrid Cascode compensation have been implemented. A common source (CS) amplifier has been used between gate and source terminals of differential input stage which further boosts the transconductance. The proposed RFC OTA is designed and simulated using 180 nm CMOS technology with load capacitance of 10 pF. It provides an excellent dc gain of 112.61 dB and gain bandwidth product (GBW) of 25.88 MHz along with 88.14<sup>0</sup> phase margin. The proposed circuit dissipates 124.66 μW of power at ± 0.5V supply voltage. The Monte Carlo analysis against device mismatch has also been performed to prove robustness of the proposed circuit.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102296"},"PeriodicalIF":2.2,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142444707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multi-bit error detection and correction technique using HVDK (Horizontal-Vertical-Diagonal-Knight) parity 使用 HVDK（水平-垂直-对角-骑士）奇偶校验的多比特错误检测和纠正技术

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-10-10 DOI: 10.1016/j.vlsi.2024.102297

Abdul Aziz , Md. Asaf-uddowla Golap , Md. Rahat Ebne Alamgir Porosh , Md. Tasnimul Khair Tousif , Muhammad Sheikh Sadi

{"title":"Multi-bit error detection and correction technique using HVDK (Horizontal-Vertical-Diagonal-Knight) parity","authors":"Abdul Aziz , Md. Asaf-uddowla Golap , Md. Rahat Ebne Alamgir Porosh , Md. Tasnimul Khair Tousif , Muhammad Sheikh Sadi","doi":"10.1016/j.vlsi.2024.102297","DOIUrl":"10.1016/j.vlsi.2024.102297","url":null,"abstract":"<div><div>In a data stream, errors are quite likely to occur and sometimes this is much more terrible. So, data safety is very important in digital systems, especially in critical and real-time systems, microprocessors, embedded systems, computer memory, and data communication. The probability of soft error increases with the exponential rate of increasing transistor per chip, operational voltage, particle strike, condensation of bit-cell area, etc. To ensure data integrity, safety, and system reliability, error detection, and correction are fundamental components of data transmission and storage systems. Existing error correction techniques can solve several bits of error. However, these existing methods are not fully efficient, as some consume a lot of time, space, and bit overhead. An ideal approach will have the potential to minimize all of these parameters. This research paper proposes a novel error correction approach with horizontal, vertical, diagonal, and knight (HVDK) parity bits. This approach has been taken to correct 5-bit errors in 64 bits of data word using the parity-based technique with less bit overhead. Our research advances the knowledge of error correction methods and sheds light on how to pick and use parity bit schemes that are appropriate for different applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102297"},"PeriodicalIF":2.2,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142530089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low-power common-mode insensitive rail-to-rail dynamic comparator for ADCs 用于 ADC 的低功耗共模不敏感轨至轨动态比较器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-10-05 DOI: 10.1016/j.vlsi.2024.102288

Nidhi Sharma , Rajesh Kumar Srivastava , Deep Sehgal , Devarshi Mrinal Das

{"title":"A low-power common-mode insensitive rail-to-rail dynamic comparator for ADCs","authors":"Nidhi Sharma , Rajesh Kumar Srivastava , Deep Sehgal , Devarshi Mrinal Das","doi":"10.1016/j.vlsi.2024.102288","DOIUrl":"10.1016/j.vlsi.2024.102288","url":null,"abstract":"<div><div>This paper presents a low-power, high-speed dynamic comparator with a rail-to-rail input common-mode (<span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>i</mi><mo>,</mo><mi>c</mi><mi>m</mi></mrow></msub></math></span>) range. The proposed comparator has high-speed performance throughout the 0-Vdd <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>i</mi><mo>,</mo><mi>c</mi><mi>m</mi></mrow></msub></math></span> range, thus attributing common-mode insensitivity. This work introduces a merger of NMOS and PMOS dynamic pre-amplifiers with a modified latch to achieve the rail-to-rail <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>i</mi><mo>,</mo><mi>c</mi><mi>m</mi></mrow></msub></math></span> operation. A novel activation clock logic is also proposed, activating only one pre-amplifier based on the <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>i</mi><mo>,</mo><mi>c</mi><mi>m</mi></mrow></msub></math></span> value and ensuring low-power consumption and provides reduction of 17% in the energy per conversion as compared to the comparator without activation clock logic. The proposed comparator is designed using 65-nm CMOS technology with a 1.2 V supply voltage and is operating at 1 GHz frequency. We have presented the analytical models of the delay and offset which is verified with the rigorous post-layout simulation results. To validate the robustness of the proposed comparator, the PVT corner analysis with Monte Carlo simulation is also performed for different <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>i</mi><mo>,</mo><mi>c</mi><mi>m</mi></mrow></msub></math></span>.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102288"},"PeriodicalIF":2.2,"publicationDate":"2024-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142419985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Decomposition based estimation of distribution algorithm for high-level synthesis design space exploration 探索高级合成设计空间的基于分解的分布估计算法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-10-05 DOI: 10.1016/j.vlsi.2024.102292

Yuan Yao, Huiliang Hong, Shanshan Wang, Chenglong Xiao

{"title":"Decomposition based estimation of distribution algorithm for high-level synthesis design space exploration","authors":"Yuan Yao, Huiliang Hong, Shanshan Wang, Chenglong Xiao","doi":"10.1016/j.vlsi.2024.102292","DOIUrl":"10.1016/j.vlsi.2024.102292","url":null,"abstract":"<div><div>High-Level Synthesis (HLS) has evolved significantly due to the increasing complexity of integrated circuit design and the demand for efficient design methodologies. HLS, which raises the abstraction level of design specification, allows designers to focus on hardware functionality, thus enhancing productivity and reducing verification efforts. However, a key challenge in HLS is efficiently exploring the vast design space to find the Pareto-optimal designs. In this paper, we introduce a novel approach for multi-objective design space exploration in HLS. Our methodology decomposes the design space exploration problem into simpler sub-problems using the Multi-Objective Evolutionary Algorithm based on Decomposition (MOEA/D) framework and utilizes the Estimation of Distribution Algorithm (EDA) to build a probabilistic model for generating candidate solutions, thereby reducing the required number of expensive synthesis runs. Experimental results show that the proposed method has a faster convergence speed and reduces the number of syntheses by 24.34% to 32.01%, which significantly outperforms state-of-the-art works. Our approach achieves superior Pareto fronts with the lowest average ADRS value, outperforming Lattice-expl, <span><math><mi>ϵ</mi></math></span> -Constraint GA, and NSGA-II by 85.64%, 39.90%, and 33.31% respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102292"},"PeriodicalIF":2.2,"publicationDate":"2024-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142419989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Learning placement order for constructive floorplanning 建设性平面规划的学习安置顺序

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-10-02 DOI: 10.1016/j.vlsi.2024.102293

Weiqiang Yao , Yibo Lin , Lin Li

{"title":"Learning placement order for constructive floorplanning","authors":"Weiqiang Yao , Yibo Lin , Lin Li","doi":"10.1016/j.vlsi.2024.102293","DOIUrl":"10.1016/j.vlsi.2024.102293","url":null,"abstract":"<div><div>Floorplanning is an early and essential task of physical design. Recently, there has been a surge in the application of learning-based methods to tackle floorplanning problem. A prevalent approach involves training a reinforcement learning (RL) agent to sequentially place blocks on a chip canvas. However, existing methods mainly focus on learning block placement, relying on heuristic rules for placement order determination. In contrast to previous approaches, we propose an RL-based method to determine the placement order. Based on block features and states, an agent is trained to select the block for placement. Once a block is selected, we enumerate all potential relative positions captured by sequence pairs and select the optimal placement. After establishing the layout topology, we further optimize wirelength through linear programming. Experimental results demonstrate the effectiveness of our proposed method. On the original-outline MCNC benchmarks, our method achieves a notable 25.2% average improvement in wirelength compared to a recent learning-based method. Additionally, when applied to rescaled-outline benchmarks from MCNC and GSRC, our method outperforms state-of-the-art results, resulting in an average wirelength reduction of 12.5%.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102293"},"PeriodicalIF":2.2,"publicationDate":"2024-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142432447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multi-frequency weak signal detection based on Liu-like chaotic synchronization system and its hardware circuit implementation 基于类刘混沌同步系统的多频微弱信号检测及其硬件电路实现

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-27 DOI: 10.1016/j.vlsi.2024.102290

Shaohui Yan, Zihao Guo, Jincai Song

{"title":"Multi-frequency weak signal detection based on Liu-like chaotic synchronization system and its hardware circuit implementation","authors":"Shaohui Yan, Zihao Guo, Jincai Song","doi":"10.1016/j.vlsi.2024.102290","DOIUrl":"10.1016/j.vlsi.2024.102290","url":null,"abstract":"<div><div>Considering the shortcomings of traditional chaotic systems in weak signal detection methods, such as the high threshold sensitivity requirement and the narrow detection frequency domain. This study proposes a novel three-dimensional chaotic synchronization system, and the dynamical of the system are exhaustively characterized using equilibrium points, phase diagrams, Lyapunov exponential spectra, and bifurcation diagrams. This method involves weak signal detection by means of chaotic synchronization control. Synchronization of a chaotic system using a backstepping synchronization method is used to detect weak signals by analyzing the synchronization error after the introduction of weak signals in a strong noise background. The chaotic system is implemented by hardware circuits, and the simulation of chaotic synchronization control and detection of weak signals from the perspective of circuits is carried out by circuit simulation software. Additionally, the frequency range within which the system is capable of weak signal detection is tested through extensive simulation experiments. Finally, multi-frequency signals detection experiments are performed. The experimental results demonstrate that the system can accurately detect the frequency of weak signals address the limitations of narrow-band detection and multi-frequency signal detection is possible. Meanwhile, the circuit structure proposed in this paper is simple and has some value for engineering applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102290"},"PeriodicalIF":2.2,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142419988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware acceleration of Tiny YOLO deep neural networks for sign language recognition: A comprehensive performance analysis 用于手语识别的 Tiny YOLO 深度神经网络的硬件加速：综合性能分析

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-26 DOI: 10.1016/j.vlsi.2024.102287

Mohita Jaiswal, Abhishek Sharma, Sandeep Saini

引用次数: 0

A hybrid memory polynomial digital predistortion model for RF transmitters 射频发射机的混合记忆多项式数字预失真模型

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-24 DOI: 10.1016/j.vlsi.2024.102285

Jijun Ren, Ziyang Xu, Xing Wang

引用次数: 0