An efficient architecture of truncated booth multiplier for AI application

This paper presents truncated approximate booth multipliers (TR-ABMs) that are both energy- and area-efficient, leveraging novel Leading One/Zero Position Detectors (LOZPDs) and optimized approximate booth multiplier (ABM) architectures. The proposed LOZPDs enable substantial reductions in Area-Delay Product (ADP) and Power-Delay Product (PDP) relative to existing techniques. Two architectures are introduced: TR-ABM1 integrates LOZPD-based operand truncation with a conventional Booth multiplier, while TR-ABM2 employs an approximate Booth multiplier variant for further efficiency gains. The level of approximation is tunable through key design parameters, including multiplier width ($w$) and the number of partial product columns utilizing Approximate Partial Product Generators (APGs) and Approximate Compressors (ACs). Comprehensive error analysis is conducted via Monte Carlo simulations with 10 million random inputs, and the designs are synthesized using Cadence® Genus in 90 nm CMOS technology. The TR-ABMs are evaluated in neural network (NN) inference and 64-point Fast Fourier Transform (FFT64) applications. For MNIST handwritten digit classification, the TR-ABMs achieve accuracy on par with exact fixed-point Booth multipliers. In FFT64, the proposed designs deliver significant area and power savings over state-of-the-art approximate multipliers. Specifically, the TR-ABMs achieve 66.58%–75.59% reductions in ADP and 47.91%–60.94% reductions in PDP, while maintaining reliable computational accuracy. Overall, the TR-ABMs offer a superior accuracy-performance trade-off compared to prior approximate multipliers, making them highly suitable for energy-efficient artificial intelligence and signal processing applications.