An Adaptive Congestion-aware Approximate Communication (ACAC) scheme and implementation for Network-on-Chip systems

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Shize Zhou , Wenjie Fan , Siyue Li , Yongqi Xue , Shiping Li , Songfeng Deng , Jinlun Ji , Tong Cheng , Xinyu Wang , Li Li , Yuxiang Fu
{"title":"An Adaptive Congestion-aware Approximate Communication (ACAC) scheme and implementation for Network-on-Chip systems","authors":"Shize Zhou ,&nbsp;Wenjie Fan ,&nbsp;Siyue Li ,&nbsp;Yongqi Xue ,&nbsp;Shiping Li ,&nbsp;Songfeng Deng ,&nbsp;Jinlun Ji ,&nbsp;Tong Cheng ,&nbsp;Xinyu Wang ,&nbsp;Li Li ,&nbsp;Yuxiang Fu","doi":"10.1016/j.vlsi.2025.102561","DOIUrl":null,"url":null,"abstract":"<div><div>Data-intensive applications like machine learning and pattern recognition impose heavy Network-on-Chip (NoC) communication loads, drastically increasing on-chip latency. Leveraging the error-tolerant nature of such applications, this paper proposes the Adaptive Congestion-Aware Approximate Communication (ACAC) scheme to dynamically balance approximation and reliability by detecting congestion distribution through three integrated strategies — source control (adjusting approximation rates at the source node), on-the-way control (refining decisions at intermediate routers), and a combined strategy. Cycle-accurate simulations shows a 6% to 36% saturated injection rate improvement over ABDTR under synthetic traffic and superior comprehensive performance across all strategies in real-application traces, particularly with the combined strategy achieving the best results while reducing additional control traffic by 52% compared to ABDTR. Despite these enhancements, the suggested framework incurs minimal hardware overhead, with only a 7.42% area increase and 7.79% power consumption rise relative to traditional NoC designs, demonstrating its potential as a scalable, application-aware solution for energy-efficient NoC optimization in error-resilient domains.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102561"},"PeriodicalIF":2.5000,"publicationDate":"2025-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025002184","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

Abstract

Data-intensive applications like machine learning and pattern recognition impose heavy Network-on-Chip (NoC) communication loads, drastically increasing on-chip latency. Leveraging the error-tolerant nature of such applications, this paper proposes the Adaptive Congestion-Aware Approximate Communication (ACAC) scheme to dynamically balance approximation and reliability by detecting congestion distribution through three integrated strategies — source control (adjusting approximation rates at the source node), on-the-way control (refining decisions at intermediate routers), and a combined strategy. Cycle-accurate simulations shows a 6% to 36% saturated injection rate improvement over ABDTR under synthetic traffic and superior comprehensive performance across all strategies in real-application traces, particularly with the combined strategy achieving the best results while reducing additional control traffic by 52% compared to ABDTR. Despite these enhancements, the suggested framework incurs minimal hardware overhead, with only a 7.42% area increase and 7.79% power consumption rise relative to traditional NoC designs, demonstrating its potential as a scalable, application-aware solution for energy-efficient NoC optimization in error-resilient domains.
片上网络系统的自适应拥塞感知近似通信(ACAC)方案及其实现
像机器学习和模式识别这样的数据密集型应用程序施加了沉重的片上网络(NoC)通信负载,大大增加了片上延迟。利用此类应用的容错特性,本文提出了自适应拥塞感知近似通信(ACAC)方案,通过三种集成策略——源控制(在源节点调整近似速率)、路上控制(在中间路由器改进决策)和组合策略来检测拥塞分布,从而动态平衡近似和可靠性。周期精确模拟表明,在综合流量下,ABDTR的饱和注入速率比ABDTR提高了6%至36%,在实际应用中,所有策略的综合性能都优于ABDTR,特别是与ABDTR相比,组合策略取得了最佳效果,同时减少了52%的额外控制流量。尽管有这些改进,但所建议的框架所带来的硬件开销最小,与传统的NoC设计相比,仅增加了7.42%的面积和7.79%的功耗,这表明它有潜力成为一种可扩展的、应用感知的解决方案,用于在容错领域进行节能NoC优化。
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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