Fine-grained data integration for high throughput and bandwidth-efficient computation on FPGAs

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2025-09-23 DOI:10.1016/j.vlsi.2025.102563

Jiyuan Liu , Baoping Wang , Yongming Tang , He Li

引用次数: 0

Abstract

The surge in terabit-scale computational workloads in AI, smart grids, and scientific computing exacerbates bandwidth bottlenecks in high-performance computing (HPC) infrastructures. Existing solutions have focused on computational architecture optimizations or hardware upgrades, neglecting inefficiencies in data distribution patterns during bus transfers. To solve these issues with maintaining data integrity and bus alignment, we propose a fine-grained data integration (FDI) accelerator on FPGAs based on the proposed adaptive window selection method and data integration algorithm. Evaluated on exemplary HPC workloads, FDI achieves up to 43.8% bandwidth improvements without computational architectural modifications while maintaining at least 22.0% optimizations for data transfer across diverse data streams without altering existing bus protocols or architectures.

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在fpga上实现高吞吐量和带宽效率计算的细粒度数据集成

人工智能、智能电网和科学计算中太比特级计算工作量的激增加剧了高性能计算（HPC）基础设施的带宽瓶颈。现有的解决方案侧重于计算体系结构优化或硬件升级，而忽略了总线传输期间数据分布模式的低效率。为了解决这些问题，保持数据完整性和总线对齐，我们提出了一种基于自适应窗口选择方法和数据集成算法的fpga上的细粒度数据集成加速器。在典型的HPC工作负载上进行评估，FDI在不修改计算架构的情况下实现了高达43.8%的带宽改进，同时在不改变现有总线协议或架构的情况下，在不同数据流之间保持了至少22.0%的数据传输优化。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.