一种基于单DDCC的无损浮动电容乘法器

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2025-09-17 DOI:10.1016/j.vlsi.2025.102560

Tolga Yucehan , Erkan Yuce , Shahram Minaei , Costas Psychalinos

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引用次数: 0

摘要

本文提出了一种采用单反相差分电流传送带（DDCC -）的新型无损浮电容倍增器（FCM）。DDCC−的内部结构只使用了16个MOS晶体管。所提出的FCM包括标准数量的无源元件。所提出的FCM不需要无源元素匹配要求。所提出的FCM具有低功耗，并且倍增系数为500，其工作频率范围从大约22 mHz扩展到500 kHz。仿真结果表明，工作频率范围不受温度变化的影响。应用实例和ad844对该FCM进行了测试。利用SPICE程序完成了所有的仿真。

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A lossless floating capacitance multiplier based on the single DDCC−

In this paper, a new lossless floating capacitance multiplier (FCM) using a single inverting type differential difference current conveyor (DDCC−) is proposed. Only 16 MOS transistors are used in the internal structure of the DDCC−. The proposed FCM includes a canonical number of passive components. Passive element matching requirements are unnecessary for the proposed FCM. The proposed FCM exhibits low power dissipation, and for a multiplication factor of 500, its operating frequency range extends from approximately 22 mHz to 500 kHz. Simulation results indicate that the operating frequency range remains unaffected with the temperature variations. The proposed FCM is tested in the application example and experimentally with AD844s. All simulations by using the SPICE program are accomplished.

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.