Shize Zhou , Wenjie Fan , Siyue Li , Yongqi Xue , Shiping Li , Songfeng Deng , Jinlun Ji , Tong Cheng , Xinyu Wang , Li Li , Yuxiang Fu
{"title":"片上网络系统的自适应拥塞感知近似通信(ACAC)方案及其实现","authors":"Shize Zhou , Wenjie Fan , Siyue Li , Yongqi Xue , Shiping Li , Songfeng Deng , Jinlun Ji , Tong Cheng , Xinyu Wang , Li Li , Yuxiang Fu","doi":"10.1016/j.vlsi.2025.102561","DOIUrl":null,"url":null,"abstract":"<div><div>Data-intensive applications like machine learning and pattern recognition impose heavy Network-on-Chip (NoC) communication loads, drastically increasing on-chip latency. Leveraging the error-tolerant nature of such applications, this paper proposes the Adaptive Congestion-Aware Approximate Communication (ACAC) scheme to dynamically balance approximation and reliability by detecting congestion distribution through three integrated strategies — source control (adjusting approximation rates at the source node), on-the-way control (refining decisions at intermediate routers), and a combined strategy. Cycle-accurate simulations shows a 6% to 36% saturated injection rate improvement over ABDTR under synthetic traffic and superior comprehensive performance across all strategies in real-application traces, particularly with the combined strategy achieving the best results while reducing additional control traffic by 52% compared to ABDTR. Despite these enhancements, the suggested framework incurs minimal hardware overhead, with only a 7.42% area increase and 7.79% power consumption rise relative to traditional NoC designs, demonstrating its potential as a scalable, application-aware solution for energy-efficient NoC optimization in error-resilient domains.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102561"},"PeriodicalIF":2.5000,"publicationDate":"2025-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Adaptive Congestion-aware Approximate Communication (ACAC) scheme and implementation for Network-on-Chip systems\",\"authors\":\"Shize Zhou , Wenjie Fan , Siyue Li , Yongqi Xue , Shiping Li , Songfeng Deng , Jinlun Ji , Tong Cheng , Xinyu Wang , Li Li , Yuxiang Fu\",\"doi\":\"10.1016/j.vlsi.2025.102561\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>Data-intensive applications like machine learning and pattern recognition impose heavy Network-on-Chip (NoC) communication loads, drastically increasing on-chip latency. Leveraging the error-tolerant nature of such applications, this paper proposes the Adaptive Congestion-Aware Approximate Communication (ACAC) scheme to dynamically balance approximation and reliability by detecting congestion distribution through three integrated strategies — source control (adjusting approximation rates at the source node), on-the-way control (refining decisions at intermediate routers), and a combined strategy. Cycle-accurate simulations shows a 6% to 36% saturated injection rate improvement over ABDTR under synthetic traffic and superior comprehensive performance across all strategies in real-application traces, particularly with the combined strategy achieving the best results while reducing additional control traffic by 52% compared to ABDTR. Despite these enhancements, the suggested framework incurs minimal hardware overhead, with only a 7.42% area increase and 7.79% power consumption rise relative to traditional NoC designs, demonstrating its potential as a scalable, application-aware solution for energy-efficient NoC optimization in error-resilient domains.</div></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":\"106 \",\"pages\":\"Article 102561\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2025-09-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926025002184\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025002184","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
An Adaptive Congestion-aware Approximate Communication (ACAC) scheme and implementation for Network-on-Chip systems
Data-intensive applications like machine learning and pattern recognition impose heavy Network-on-Chip (NoC) communication loads, drastically increasing on-chip latency. Leveraging the error-tolerant nature of such applications, this paper proposes the Adaptive Congestion-Aware Approximate Communication (ACAC) scheme to dynamically balance approximation and reliability by detecting congestion distribution through three integrated strategies — source control (adjusting approximation rates at the source node), on-the-way control (refining decisions at intermediate routers), and a combined strategy. Cycle-accurate simulations shows a 6% to 36% saturated injection rate improvement over ABDTR under synthetic traffic and superior comprehensive performance across all strategies in real-application traces, particularly with the combined strategy achieving the best results while reducing additional control traffic by 52% compared to ABDTR. Despite these enhancements, the suggested framework incurs minimal hardware overhead, with only a 7.42% area increase and 7.79% power consumption rise relative to traditional NoC designs, demonstrating its potential as a scalable, application-aware solution for energy-efficient NoC optimization in error-resilient domains.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.