Fredkin Gate-based Arbiter PUF design through challenge obfuscation using garbage outputs

Abstract

This paper presents the design and implementation of a Fredkin Gate (FRG)-based Arbiter PUF using a novel challenge obfuscation method via garbage outputs, termed Garbage-induced Challenge Preprocessing FRG-based Arbiter PUF (GCP-APUF). The approach scrambles the input challenge using garbage outputs from FRG switch blocks, which are affected by fabrication process variations, introducing uncertainty in the PUF input. A mathematical model of the design is provided. The GCP-APUF is implemented on a 28 nm Artix-7 FPGA using a 64-bit XNOR-based LFSR for challenge generation, with manually placed switch blocks and an Arbiter, producing 48-bit response outputs. The design achieves 51.51% uniformity and 47.35% uniqueness. Compared to conventional and FRG Arbiter PUFs, it shows increased uniformity by 18.94% and 5.57%, and uniqueness by 5.61% and 4.10%, respectively. Reliability, BER, and KER are 92.85%, 7.2%, and 0.955. Randomness tests are passed. Machine learning susceptibility using neural networks yields a low CRP prediction accuracy of 50.43%, indicating strong resistance.