Integration-The Vlsi Journal最新文献

{"title":"Lorenz system manufacturing with a Butterworth filter","authors":"L.L. Jiménez-Zacarías ,&nbsp;I. Campos-Cantón","doi":"10.1016/j.vlsi.2025.102386","DOIUrl":"10.1016/j.vlsi.2025.102386","url":null,"abstract":"<div><div>This paper investigates the Lorenz system <span><math><mi>x</mi></math></span> state equation duality, with a first-order <span><math><mrow><mi>R</mi><mi>C</mi></mrow></math></span> passive low-pass filter to propose a new Lorenz type system. This new Lorenz type system is done electronically; to fulfill this objective, an electronic circuit is developed using a Butterworth, Chebyshev, and second order <span><math><mrow><mi>R</mi><mi>C</mi></mrow></math></span> filter replacing the <span><math><mi>x</mi></math></span> state low pass filter. The electronic circuit is simulated using Multisim software. Bifurcation diagrams, Lyapunov exponents, and phase portrait techniques are used to confirm the chaotic circuit behavior. It is found that the Lorenz system produces chaos if the second-order <span><math><mrow><mi>R</mi><mi>C</mi></mrow></math></span> filter associated with the <span><math><mi>x</mi></math></span> state is tuned to a 10 rad/sec cutoff frequency, whereas it should be 28 rad/sec for the Butterworth filter and 40 rad/sec for the Chebyshev filter.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102386"},"PeriodicalIF":2.2,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143526810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamics analysis and DSP implementation of a new four-dimensional discrete memristor hyperchaotic map","authors":"Chenkai Zhang,&nbsp;Huibin Wang,&nbsp;Yiyan Zhang,&nbsp;Lili Zhang,&nbsp;Chunyan Ma","doi":"10.1016/j.vlsi.2025.102384","DOIUrl":"10.1016/j.vlsi.2025.102384","url":null,"abstract":"<div><div>In recent years, discrete memristors have garnered significant interest from the scientific community due to their nonlinear and adaptive properties. These characteristics make them ideal for use as nonlinear elements in generating chaotic oscillations. However, the current research on the discrete memristor chaotic map is still focused on constructing it by coupling first-order discrete memristors, and the research on coupling higher-order discrete memristors is relatively limited. This paper presents a novel four-dimensional discrete memristor hyperchaotic map that is coupled with a second-order discrete memristor. Through numerical simulations, we analyze the bifurcation diagram and Lyapunov index diagram of the new map with the change of coupling coefficient and various control parameters. Our findings indicate that the map exists in a hyperchaotic state and demonstrates the coexistence of multiple attractors under varying initial conditions. This results in a rich tapestry of dynamic behaviors and high complexity. Moreover, we have implemented the memristor chaotic map by DSP platform.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102384"},"PeriodicalIF":2.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143529079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lightweight FPGA acceleration framework for structurally tailored multi-version MobileNetV1","authors":"XuMing Lu,&nbsp;JiaWei Zhang,&nbsp;LuoJie Zhu,&nbsp;XianYang Tan","doi":"10.1016/j.vlsi.2025.102383","DOIUrl":"10.1016/j.vlsi.2025.102383","url":null,"abstract":"<div><div>Convolutional neural networks (CNNs) have significantly enhanced image recognition performance through effective feature extraction and weight sharing, establishing themselves as a pivotal research area in computer vision. Despite these advances, CNNs demand substantial computational resources, posing challenges for deployment on resource-constrained embedded devices. Consequently, lightweight CNN models, such as MobileNet, have been developed to optimize computational efficiency. However, these models still necessitate accelerators to achieve optimal performance. Field-programmable gate arrays (FPGAs) present a viable solution for accelerating lightweight CNN models, thanks to their inherent capabilities for high parallelism, superior energy efficiency compared to traditional CPUs or GPUs, and reconfigurability, which adapts well to evolving network architectures. Nevertheless, compact FPGAs are limited by their on-chip logic resources. This limitation, coupled with the requirement to support multiple pruned versions of MobileNet networks due to advancements in model structure pruning, complicates the FPGA design process and escalates the resource allocation and associated costs. To address this issue, we propose a master-slave architecture for the MobileNetV1 computing framework, where the master module manages task scheduling and resource allocation, while slave modules execute the actual convolutional computations. This framework employs a dynamic configuration method, programming execution parameters for each network layer into the FPGA, allowing adaptability and optimization of resource usage. The proposed design was validated on the Altera De2-115 FPGA evaluation board using the MobileNet-V1-0.5-160 model. Experimental results demonstrated that, when implemented on the Altera De2-115 FPGA board, the recognition speed of our optimized MobileNetV1 model could reach 68.9 frames per second (FPS) with an 8-bit data width and a clock speed of 25 MHz, utilizing only 38K logic units—an efficient performance benchmark compared to previous FPGA implementations.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102383"},"PeriodicalIF":2.2,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143526809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Synchronization in scale-free neural networks with heterogeneous time delay","authors":"JiaXin Tang ,&nbsp;YaLian Wu ,&nbsp;ChunYuan Ou ,&nbsp;Pengcheng Zhong ,&nbsp;Xue Zhao ,&nbsp;Minglin Ma","doi":"10.1016/j.vlsi.2025.102387","DOIUrl":"10.1016/j.vlsi.2025.102387","url":null,"abstract":"<div><div>The functional network of the human brain exhibits scale-free topology, and there are inevitable time delays in information transmission between neurons. This study explores the relationship between synchronization transitions and heterogeneous time delays in scale-free neuronal networks, as well as the influence of coupling strength on the synchronization process under the premise of introducing heterogeneous time delays. Inspired by small-world network construction methods, we designed a scale-free neural network model with heterogeneous time delays based on the Rulkov neuron model, referred to as the Heterogeneous Scale-Free Neural Network (HSFNN). In this paper, we propose a time delay determination mechanism (TDDM). Subsequently, we conducted numerical simulations to analyze the effects of various parameters related to time delays on the synchronization of HSFNNs. The results were analyzed using spatiotemporal state diagrams, recursion diagrams, and node state diagrams. The findings indicate that HSFNNs exhibit various dynamical phenomena, such as asynchronous, synchronous, and alternating states of synchronization and asynchrony. Furthermore, we found that altering coupling strength under the premise of introducing heterogeneous time delays also affects the synchronization states of HSFNNs.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102387"},"PeriodicalIF":2.2,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143471531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA implementation of EEG based hardware optimized data encryption technique for IoT applications","authors":"Hari Krishna Kharidu,&nbsp;V. Sudha","doi":"10.1016/j.vlsi.2025.102381","DOIUrl":"10.1016/j.vlsi.2025.102381","url":null,"abstract":"<div><div>This paper has presented a new electroencephalogram (EEG)-based encryption technique for enhancing image data security using an FPGA implementation for IoT applications. The technique has used EEG datasets to create 64-bit keys, which have undergone testing using the NIST SP 800-22 test suite for randomness check. The generated keys have been combined with the image data and subjected to substitution and LFSR-based permutation in a proposed order. The proposed method has implemented the RTL design on a Virtex-7 FPGA device, with careful selection of rounds to optimize encryption process efficiency. The hardware expenditure per round on the FPGA device has been assessed to determine the optimal limit on the number of rounds, and the simulation results have been validated using MATLAB. The parameters Number of Changing Pixel Rate (NPCR) and Unified Averaged Changed Intensity (UACI) have been calculated as 99.5697% and 33.4776%, respectively, while the entropy of the encrypted image is 7.95, indicating that the suggested approach exhibits greater resilience against differential attacks. The proposed method has achieved a maximum operating frequency of 815.395 MHz and efficiency of 5.623 Mbps/slice on Virtex-7 FPGA device which has exhibited a 49.95% increase in the maximum frequency of operation and a 7.11% gain in efficiency when compared with the state of the art. These improvements have been important for reducing the encryption time and efficiently utilizing the hardware with the optimum number of slices.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102381"},"PeriodicalIF":2.2,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143473998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"JoBiS: Joint capacitance and inductance bit stuffing CAC for interposer based multi-chip Deep Learning Accelerator","authors":"Zahra Shirmohammadi,&nbsp;Masoumeh Taali","doi":"10.1016/j.vlsi.2025.102347","DOIUrl":"10.1016/j.vlsi.2025.102347","url":null,"abstract":"<div><div>Interposer-based multi-chip Deep Learning Accelerator (DLA) profoundly influences the design of artificial intelligence (AI) hardware. However, data transmission over wires in Network-on-Chip (NoC)-based Deep Learning Accelerators (DLAs) encounters crosstalk faults as a major challenge. These faults arise due to mutual capacitance and inductance influences between adjacent wires of the NoCs. To address this issue, this paper introduces JoBiS, a bit-stuffing algorithm that takes into account both capacitance and inductance coupling effects. JoBiS aims to prevent the occurrence of the worst delay transitions in inductance coupling, such as 00000<span><math><mrow><mo>→</mo><mn>11111</mn><mo>,</mo><mn>11111</mn><mo>→</mo></mrow></math></span>00000, and 00-00<span><math><mo>→</mo></math></span>11-11, as well as in capacitive coupling, including 11-11<span><math><mo>→</mo></math></span>00-00, 01010<span><math><mo>→</mo></math></span>10101, and 10101<span><math><mo>→</mo></math></span>01010, in a 5-bit wire model. This is achieved through a simple and low-power algorithm. To reduce delay and area overhead in large buses, a bus partitioning-based CAC called JoBiS is proposed. The simulation results indicate that the power consumption and delay are significantly improved compared to other methods. On average, JoBiS reduces power consumption and critical path delay by 83% and 70%, respectively, across various bus widths.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102347"},"PeriodicalIF":2.2,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143395413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Transimpedance amplifiers for large-area and ultrahigh bandwidth high-energy particle detectors","authors":"Jiayi Wang ,&nbsp;Yichen Zhang ,&nbsp;Yuanjun Guan ,&nbsp;Tao Wang ,&nbsp;Qianchuan Yi ,&nbsp;Wenxin Jiang ,&nbsp;Xiaopu Gu ,&nbsp;Li Zhang ,&nbsp;Binbing Huang ,&nbsp;Tianyan Han ,&nbsp;Lilei Hu","doi":"10.1016/j.vlsi.2025.102382","DOIUrl":"10.1016/j.vlsi.2025.102382","url":null,"abstract":"<div><div>In the realm of high-energy particle detection, a trade-off exists between achieving a large sensitive area and ensuring high-speed detector response. Current methodologies, such as negative Miller capacitance, have made progress in enhancing both detection area and response speed. Nevertheless, these designs frequently suffer from limitations in parasitic capacitance, especially with large detection areas, which ultimately constrains bandwidth. This study introduces a segmented-integration method combined with optimized front-end circuits to overcome these challenges. By segmenting a single large sensitive area into smaller pixels, each coupled with an independent front-end transimpedance amplifier (TIA), this design can significantly enhance the response speed while maintaining a large sensitive area. Although it complicates the overall system, the output signals from each pixel are summed to preserve the detector's large-area capability. This study has developed novel front-end circuits for both linear and Geiger modes, offering exceptional performance in terms of detector gain and bandwidth. In linear mode, a multi-channel TIA is designed to handle up to 32 pixels simultaneously, providing a gain of 50 dBΩ and 450 MHz bandwidth despite 160 pF parasitic capacitance. For Geiger mode, a novel TIA with a feedforward is proposed, providing a gain of 70 dBΩ and 450 MHz bandwidth for a pixel with a 5 pF parasitic capacitance without the need for compensating capacitors. To enable rapid single-particle counting, a four-delay trigger sampling comparator structure is designed with a sampling rate reaching 4 GS/s under process limitation. The circuits are designed in 180 nm CMOS process and verified through Sentaurus and Cadence simulation software, demonstrating excellent performance with a 68.8 mm² detection area and an ultrahigh cutoff frequency of 450 MHz.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102382"},"PeriodicalIF":2.2,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143445044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High throughput true random number generator based on dynamically superimposed hybrid entropy sources","authors":"Yingchun Lu ,&nbsp;Changlong Cao ,&nbsp;Yang Liu ,&nbsp;Huaguo Liang ,&nbsp;Liang Yao ,&nbsp;Lixiang Ma","doi":"10.1016/j.vlsi.2025.102380","DOIUrl":"10.1016/j.vlsi.2025.102380","url":null,"abstract":"<div><div>True random number generator is a crucial hardware system component that is widely used in the fields of cryptographic communication, key generation, statistical simulation, and secure authentication. However, the related TRNG suffers from low throughput and high resource overhead due to relying on a single entropy source. To address this issue, a TRNG circuit implementation scheme based on a MUX-XOR gate cell (MX-cell) is proposed, which uses the switching characteristics of the MUX and the XOR gate to generate metastability and jitter to develop a hybrid entropy source. It further enables the dynamic superposition of entropy sources under prescribed conditions, which improves the TRNG throughput while reducing the resource overhead. The proposed TRNG is implemented on Xilinx Artix-7 and Kintex-7 FPGAs with automatic placement and routing, passing NIST, AIS-31, TESTU01 statistical test suites and a series of other performance tests without post-processing. The experimental results reveal that the suggested design consumes only 19 LUTs, 8 DFFs, and 4 MUXs to provide random numbers with up to 380 Mbps throughput, which demonstrates highly efficient resource utilization compared to advanced published TRNGs.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102380"},"PeriodicalIF":2.2,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143395412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Chaos-based authentication of encrypted images under MQTT for IoT protocol","authors":"José David Rodríguez-Muñoz ,&nbsp;Esteban Tlelo-Cuautle ,&nbsp;Luis Gerardo de la Fraga","doi":"10.1016/j.vlsi.2025.102378","DOIUrl":"10.1016/j.vlsi.2025.102378","url":null,"abstract":"<div><div>In lightweight cryptographic applications, the authentication of encrypted data is a challenge that can be solved by using high-order chaotic systems. The proposed work shows that increasing the length of bits in a Hash function, leads to diminish the possibility of a collision. Using high-order chaotic systems, can also lead to use large prime numbers by exploiting the fact that the division and modulo operations provide a better distribution in a most uniform way. In addition, because a prime number has factors including 1 and himself, then this greatly reduces the appearance of repetitive patterns in a modulo operation. In this manner, this article presents the implementation of a chaos based system for authentication of encrypted RGB images using Raspberry Pi devices. First, a two dimensional (2D) map, and 3D, and 4D chaotic systems, are implemented on Raspberry Pi devices to design pseudo-random number generators (PRNG). Second, the randomness of the sequences is evaluated by performing NIST (National Institute of Standards and Technology) tests. Third, the random sequences are used to construct a stream cipher and an authenticated Hash function based on a method called pseudo dot product. Fourth, RGB images are encrypted using the PRNGs based on 2D, 3D, and 4D chaotic systems. In the proposed work, all these processes are performed under a machine-to-machine (M2M) wireless connectivity system, which is available on the message queuing telemetry transport (MQTT) communication protocol for Internet of Things (IoT). In the experiments, three Raspberry Pi devices are configured as a publisher, a broker, and a subscriber to work on MQTT for sending and receiving encrypted RGB images, while the images are authenticated through the evaluation of Hash function tags, which are generated by using 2D, 3D, and 4D chaotic systems. The main conclusion is that the encryption/decryption and authentication processes are much better when using high-dimensional chaotic systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102378"},"PeriodicalIF":2.2,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143372516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Intra-class CutMix data augmentation based deep learning side channel attacks","authors":"Runlian Zhang ,&nbsp;Yu Mo ,&nbsp;Zhaoxuan Pan ,&nbsp;Hailong Zhang ,&nbsp;Yongzhuang Wei ,&nbsp;Xiaonian Wu","doi":"10.1016/j.vlsi.2025.102373","DOIUrl":"10.1016/j.vlsi.2025.102373","url":null,"abstract":"<div><div>CutMix data augmentation can provide a large amount of augmented data for DL-SCA (deep learning side channel attacks) by generating new power traces. However, traces generated by CutMix may lose dependency with the new label, which may reduce the accuracy of the training model. In light of this, we propose an improved intra-class CutMix data augmentation method. Firstly, the original traces are classified by the label. Then, the original traces are selected by the same label constraint to generate new traces according to CutMix, which can ensure the dependency between the generated trace and its label. Furthermore, in order to maintain balance among different classified datasets, the traces are generated sequentially according to distinct labels. Finally, based on the augmented traces, the Multilayer Perceptron (MLP) and Convolutional Neural Network (CNN) models can be constructed and trained to recover the key of AES. In order to verify the effectiveness of the proposed method, we conduct experimental evaluations using the MLP and CNN models based on DPA-contest v4 dataset and ASCAD dataset. The test results show that the traces generated with the intra-class CutMix method can be very similar to the original traces, and the MLP and CNN models can be effectively trained based on the generated traces to recover the key of AES. Besides, compared with existing data augmentation methods, the proposed method can complete secret key recovery with faster convergence and fewer traces.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102373"},"PeriodicalIF":2.2,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}