Integration-The Vlsi Journal最新文献

{"title":"Innovative nonlinear component generator inspired by squirrel search algorithm","authors":"Fırat Artuğer","doi":"10.1016/j.vlsi.2025.102466","DOIUrl":"10.1016/j.vlsi.2025.102466","url":null,"abstract":"<div><div>The most used approach for data encryption is block cipher. One of the most important structures for block cipher algorithms is undoubtedly s-boxes. The s-box structure used in the AES algorithm contains 256 values. Therefore, obtaining powerful s-boxes is a rather difficult search problem. Because the search space is very large (256!). In this study, a new method based on squirrel search algorithm (SSA) is proposed to overcome this problem. The proposed method is displacement-based. In an s-box taken at the entrance, stronger s-box structures are sought by changing the location of the elements. The most important innovation in this study is that the elements to be displaced in the s-box were selected with the positioning states of the SSA. The chaotic Gompertz map was used for the initial population. Four different s-boxes were produced with the method developed thanks to the effective positioning states of SSA. As the fitness function, the nonlinearity value, which is the most important evaluation criterion of an s-box structure, was used. The proposed four s-box structures increased up to 110 nonlinearity values after only 4500 iterations. Here, it has been shown that the algorithm can be effective in all s-boxes by generating four different s-boxes. Considering these results, it has been determined that the proposed method gives more effective results than most methods in the literature.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102466"},"PeriodicalIF":2.2,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144480931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-cell lightweight high-throughput TRNG based on selector clock driving and XOR feedback","authors":"Wenjing Zhang ,&nbsp;Liang Yao ,&nbsp;Yuexin Wei ,&nbsp;Wanting Sun ,&nbsp;Zhuoyang Li ,&nbsp;Peiyang Kang ,&nbsp;Zhengfeng Huang ,&nbsp;Yingchun Lu","doi":"10.1016/j.vlsi.2025.102464","DOIUrl":"10.1016/j.vlsi.2025.102464","url":null,"abstract":"<div><div>True Random Number Generators (TRNGs) play a pivotal role in encryption, digital signatures, and related fields. As the most critical component of a TRNG, the entropy source determines the quality of randomness. Current TRNGs primarily rely on specific physical randomness sources as entropy sources, but this approach struggles to balance low resource overhead and high throughput. This paper proposes a multi-cell TRNG architecture based on selector clock driving and XOR feedback to achieve high throughput and superior randomness quality. The design employs D flip-flops and combinational logic gates, utilizing multiple ring oscillators (ROs) connected to selector inputs to generate clock signals and data inputs for the D flip-flops. A feedback structure with XOR gates enhances randomness. The proposed TRNG was implemented on Xilinx Virtex-6, Spartan-6, and Artix-7 FPGA boards. Experimental results demonstrate that the TRNG achieves a throughput of 433 Mb/s using only 41 LUTs and 10 D flip-flops, while passing NIST, AIS-31, autocorrelation, TESTU01, and restart tests without post-processing.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102464"},"PeriodicalIF":2.2,"publicationDate":"2025-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144330844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"GATOR: A Graph Neural Network based Design Anomaly Predictor","authors":"Sagar Satapathy,&nbsp;Dip Sankar Banerjee","doi":"10.1016/j.vlsi.2025.102452","DOIUrl":"10.1016/j.vlsi.2025.102452","url":null,"abstract":"<div><div>Several design issues detected in the physical design stages of the Application Specific Integrated Circuits (ASIC) flow are attributed to poorly written Register Transfer Level (RTL) codes. Such issues are complex to resolve using iterative synthesis, placement optimization and engineering change orders (ECOs). As a result, design closure is delayed, impacting the overall timeline of the chip tape-out. Detection of such RTL constructs early in the design flow can help tackle the downstream issues in the physical design stages like congestion hotspots, high cell/pin density in the core area, timing degradation and timing design rule violations. This work presents a graph learning based approach to detect such design anomalies in the RTL. GATOR, a synthesis tool-independent, parameterized, and customizable framework to detect design anomalies, is presented. It allows flexibility in model generation based on the degree of strictness set by the ASIC designers. This GNN-based approach is highly accurate in detecting RTL design anomalies, with an average accuracy of 98.62% for the most strict threshold combination and an average inference time of 2.75 s, resulting in a speedup of 8.59<span><math><mo>×</mo></math></span> compared to algorithm-based checks presented in this work to determine the design anomalies, which can reduce multiple iterations in the physical design stages.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102452"},"PeriodicalIF":2.2,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144562856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SDCLR: Scalable Dual Control-Layer Routing for continuous-flow microfluidic biochips with minimized control ports","authors":"Zhisheng Chen ,&nbsp;Hongjin Su ,&nbsp;Bohan Dong ,&nbsp;Genggeng Liu ,&nbsp;Xing Huang","doi":"10.1016/j.vlsi.2025.102445","DOIUrl":"10.1016/j.vlsi.2025.102445","url":null,"abstract":"<div><div>Recent advancements in continuous-flow microfluidic biochips have led to highly integrated lab-on-a-chip systems with complex functionality and minimized control ports. Despite these advancements, achieving efficient control-layer routing under strict valve synchronization remains a significant challenge. Clustering more valves into the same group can reduce the usage of control ports but necessitates building a larger routing tree to meet the length-matching requirements of synchronized valve groups, significantly reducing the routing resources available for other valves and diminishing routing feasibility. To strike an optimized balance between control port usage and routing feasibility, this paper proposes a scalable dual-control layer routing method called SDCLR, aimed at optimizing routing feasibility while minimizing the number of control ports. The main features of SDCLR include a DBSCAN-based valve readdressing to optimize routing area allocation, a conflict-aware layer assignment to minimize resource contention, and a synchronized-driven routing framework to ensure precise synchronized valve operations. Experimental results show that SDCLR performs excellently in terms of routability, control port number, and timing requirements.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102445"},"PeriodicalIF":2.2,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144364857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Testing and fault tolerance techniques for carbon nanotube-based FPGAs","authors":"Siyuan Lu ,&nbsp;Kangwei Xu ,&nbsp;Peng Xie ,&nbsp;Rui Wang ,&nbsp;Yuanqing Cheng","doi":"10.1016/j.vlsi.2025.102444","DOIUrl":"10.1016/j.vlsi.2025.102444","url":null,"abstract":"<div><div>As the semiconductor manufacturing process technology node shrinks into the nanometer-scale, the CMOS-based Field Programmable Gate Arrays (FPGAs) face big challenges in scalability of performance and power consumption. Multi-walled Carbon Nanotube (MWCNT) serves as a promising candidate for Cu interconnects thanks to the superior conductivity. Moreover, Carbon Nanotube Field Transistor (CNFET) also emerges as a prospective alternative to the conventional CMOS device because of high power efficiency and large noise margin. The combination of MWCNT and CNFET enables the promising CNT-based FPGAs. However, the MWCNT interconnects exhibit significant process variations due to immature fabrication process, leading to delay faults. Also, the non-ideal CNFET fabrication process may generate a few metallic CNTs (m-CNTs), rendering correlated faulty blocks. In this article, we propose a ring oscillator (RO) based testing technique to detect delay faults due to the process variation of MWCNT interconnects. Furthermore, we propose an effective testing technique for the carry chains in CLBs, and an improved circuit design based on the lookup table (LUT) is applied to speed up the fault testing of CNT-based FPGAs. In addition, we propose a testing algorithm to detect m-CNTs in CLBs. Finally, we propose a redundant spare row sharing architecture to improve the yield of CNT-based FPGA further. Experimental results show that the test time for a 6-input LUT can be reduced by 35.49% compared with conventional testing, and the proposed algorithm can achieve a high test coverage with little overhead. The proposed redundant architecture can repair the faulty segment effectively and efficiently.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102444"},"PeriodicalIF":2.2,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144312666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient CNFET-based ternary logic design with emphasis on half-adder and multiplier circuits","authors":"Najibullah Fazeli,&nbsp;Mehdi Bekrani,&nbsp;Mohammadreza Fathollahi","doi":"10.1016/j.vlsi.2025.102441","DOIUrl":"10.1016/j.vlsi.2025.102441","url":null,"abstract":"<div><div>This paper presents a novel methodology for synthesizing efficient ternary logic devices, specifically focusing on a Ternary Half-Adder (THA) and Ternary Multiplier (TMUL). A new ternary circuit design is proposed to minimize the Power-Delay Product (PDP) and reduce transistor count compared to existing approaches. Essential ternary gates, such as inverters, AND/NAND, and OR/NOR gates, along with the THA and TMUL, are implemented using Carbon Nanotube Field-Effect Transistors (CNFETs), chosen for their potential of high integration density and low intrinsic delay. Comprehensive simulations using HSPICE demonstrate significant performance improvements, including an average of 43% reduction in transistor count and an average of 83% decrease in PDP for the THA design compared to some prior topologies. The TMUL design also exhibits substantial PDP enhancements and transistor count reduction, achieving an average of 37% in transistor count and 65% in PDP enhancements, comparing with various benchmarks. These findings highlight that, despite a slight increase in power consumption, the proposed designs are well-suited for high-performance, low-delay, and compact (low-area) applications in advanced digital systems, confirming CNFETs as a promising alternative to CMOS in Multi-Valued Logic circuit design.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102441"},"PeriodicalIF":2.2,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144280457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An electronically controllable floating capacitor multiplier for low frequency applications","authors":"Burak Sakacı,&nbsp;Deniz Özenli","doi":"10.1016/j.vlsi.2025.102458","DOIUrl":"10.1016/j.vlsi.2025.102458","url":null,"abstract":"<div><div>In this study, a floating capacitor multiplier structure without any passive resistor, created using a subtractor and a multiple-output current differencing transconductance amplifier (MO-CDTA), is extensively analyzed. In this respect, the characteristic equations, operating principles, and filter applications of the structure examined are provided. For the floating capacitor multiplier structure, multiplication factor ‘k’ varies between 400 and 1200 depending on the <span><math><mrow><msub><mi>V</mi><mtext>GS</mtext></msub></mrow></math></span> voltage. Besides the tunability feature, another striking aspect of this work is the applied of three different filter structures due to the floating configuration. The cut-off frequency of the low-pass filter created with the floating capacitor multiplier ranges from 12.5 kHz to 32.6 kHz. Another application, the high-pass filter, has a cut-off frequency ranging from 58.4 kHz to 207.3 kHz. In the final band-pass filter structure applied in this study, it is demonstrated that the center frequency of filter ranging from 15.5 kHz to 33.5 kHz is suitable for low frequency operations due to the structure's tunable feature. In addition to filter applications, post-layout details including temperature, Monte Carlo, and total harmonic distortion analysis of the proposed capacitor multiplier are provided alongside the experimental results.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102458"},"PeriodicalIF":2.2,"publicationDate":"2025-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144263337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Side-channel attack resilient implementation of homomorphic encryption using elliptic curve cryptography for secure cloud computing","authors":"Parthasarathy R.,&nbsp;Saravanan P.","doi":"10.1016/j.vlsi.2025.102439","DOIUrl":"10.1016/j.vlsi.2025.102439","url":null,"abstract":"<div><div>In recent times, the amount of data exchanged between the cloud storage and the users has proliferated. The security of that data is also critical. To secure that data and to enhance its integrity, it should be encrypted before being uploaded into the cloud. In this work, a side-channel attack-secured additive homomorphic encryption is implemented using elliptic curve cryptography on an FPGA platform. An elliptic curve scalar multiplication, which is the critical component of elliptic curve cryptography, is designed in the general prime field using standard projective coordinate representation and implemented for 192, 224, and 256 bits as per the left-to-right double-and-add algorithm using radix-4 Booth-encoded modular multipliers in both FPGA devices and the ASIC platform. A minimum of 8242 slices is required to implement the proposed 256-bit elliptic curve scalar multiplication in the Virtex-6 FPGA device. The area of the proposed 192, 224, and 256-bit elliptic curve scalar multiplication is estimated as 149.225K, 208.178K, and 266.981 KGE in the ASIC using Cadence gpdk-45 nm technology libraries. A correlation power analysis attack is mounted on the FPGA implementation of the proposed elliptic curve scalar multiplication with an 8-bit data size to determine the value of scalar ‘n’. The attack is successful with a minimum of 2301 traces, and a high correlation coefficient value is obtained. Scalar randomization is proposed and integrated with the design as a countermeasure part to thwart the correlation power analysis attack, which is successful, and hence the left-to-right double-and-add algorithm used to determine elliptic curve scalar multiplication is made secure against side-channel attacks. This secured hardware implementation of elliptic curve cryptography is utilized to encrypt the data uploaded to the cloud, where additive homomorphic encryption is employed to process the data. Hence, additive homomorphic encryption becomes side-channel attack resilient, and cloud computations are secured.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102439"},"PeriodicalIF":2.2,"publicationDate":"2025-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144263331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Memory device based on memristor-diode crossbar and control CMOS logic for spiking neural network hardware","authors":"A.N. Busygin ,&nbsp;A.D. Pisarev ,&nbsp;S. Yu Udovichenko ,&nbsp;A.H.A. Ebrahim","doi":"10.1016/j.vlsi.2025.102461","DOIUrl":"10.1016/j.vlsi.2025.102461","url":null,"abstract":"<div><div>A compact electrical circuit of a memory device based on a memristor-diode crossbar array and peripheral CMOS control logic has been developed. The peripheral logic circuit is digitally controlled and allows reading and changing the state of individual memristors. This functionality is necessary to store and transfer the synaptic states of the neural network to another neural network to avoid re-learning. Simple original electrical circuits of input and output drivers utilizing standard rectangular impulses to control memristor-diode crossbar were created. These circuits ensure the operation of the memristor matrix both as part of the hardware spiking neural network and in the modes of writing and reading the state of the memristors. Exclusion of multiple DACs and ADCs in the electrical circuits of input and output crossbar conductor drivers made it possible to significantly reduce the occupied area on the chip. On the basis of numerical modeling using the experimental characteristics of memristors the maximum size of crossbar in the developed circuit and the influence of parasitic currents on the processes of writing and reading the state of memristors are estimated. Connection of the peripheral logic circuit in the memristor leads to a limitation of the maximum size of the crossbar due to additional parasitic currents. A method of compensating the influence of parasitic currents on the process of setting memristors in a given state by varying the duration of programming pulses is proposed.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102461"},"PeriodicalIF":2.2,"publicationDate":"2025-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144240834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A lightweight general PUF framework for resisting machine learning attacks","authors":"Tianming Ni ,&nbsp;Fei Li ,&nbsp;Zhengfeng Huang ,&nbsp;Aibin Yan ,&nbsp;Senling Wang ,&nbsp;Xiaoqing Wen ,&nbsp;Mu Nie ,&nbsp;Jingchang Bian","doi":"10.1016/j.vlsi.2025.102459","DOIUrl":"10.1016/j.vlsi.2025.102459","url":null,"abstract":"<div><div>Physical Unclonable Function (PUF) is an attractive and low-cost security primitive that requires no storage and is resistant to reverse engineering. However, classical PUFs are highly vulnerable to machine learning attacks, and most attempts to resist these attacks consume excessive resources. To address this challenge, a lightweight general PUF framework is proposed in this paper. Firstly, the framework adopts segmentation processing to introduce structural nonlinearities for the purpose of self-protection. Secondly, the pre-segment response, pre-segment challenges and post-segment challenges undergo XOR processing to introduce challenges obfuscation, which greatly enhances the machine learning resistance of the PUF. In addition, for configurable RO PUF, a novel MUX-based RO (called MRO) is proposed in this paper, which can save resources by 50 %. Implementing a two-segment MRO-MRO instance based on the proposed PUF framework results in reliability, uniformity, and uniqueness that are close to the ideal values. Comprehensive experiments demonstrate that the proposed PUF has the advantages of scalable framework, low resource overhead, and strong resistance to machine learning attacks.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102459"},"PeriodicalIF":2.2,"publicationDate":"2025-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144240832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}