Integration-The Vlsi Journal最新文献_第3页

Design and hardware implementation of 4D memristive hyperchaotic map with rich initial-relied and parameter-relied dynamics 具有丰富初始相关和参数相关动态特性的 4D 记忆超混沌图的设计与硬件实现

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-08 DOI: 10.1016/j.vlsi.2024.102252

引用次数: 0

A fully floating memristor emulator with long-term memory 带长期存储器的全浮动忆阻器仿真器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-08 DOI: 10.1016/j.vlsi.2024.102254

引用次数: 0

Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs 通用门是下一代可配置环形振荡器 PUF 的基石

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-06 DOI: 10.1016/j.vlsi.2024.102257

{"title":"Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs","authors":"","doi":"10.1016/j.vlsi.2024.102257","DOIUrl":"10.1016/j.vlsi.2024.102257","url":null,"abstract":"<div><p>In the field of hardware security, the physical unclonable function (PUF) is known as a significant advancement for its unique and unclonable outputs, serving as a ‘digital fingerprint’ for electronic devices. This distinctiveness is crucial for high-security tasks such as device authentication and cryptographic key generation. The PUF's input-output combinations, known as challenge-response pairs (CRPs), are essential to its functionality. Although the Ring Oscillator (RO) PUF is notable for its security advantages and straightforward implementation, it's considered a ‘weak’ PUF due to its limited CRPs, highlighting a demand for more robust and secure PUF designs. This paper introduces a novel configurable inversion unit (CIU), integrating two universal logic gates, NAND and NOR, to be utilized in building various configurable ring oscillator (CRO) PUF models. Using the newly proposed CIU, we introduce two distinct CRO-PUF configurations. The first one includes 16-ring oscillators, while the second has 8-ring oscillators. A modified version of this CIU is introduced to increase the size of CRPs that a PUF can handle. A comprehensive assessment process of these configurations underscores the superior performance of these models across various parameters, including reliability, distinctiveness, balance, bit-aliasing, and randomness.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0167926024001214/pdfft?md5=f9db8c6a253bc1281421d28b43151fdc&pid=1-s2.0-S0167926024001214-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141963111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electronically tunable single FTFNTA-based universal memelement emulator using only grounded passive elements 仅使用接地无源元件的基于 FTFNTA 的电子可调单一通用记忆元件仿真器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-06 DOI: 10.1016/j.vlsi.2024.102253

{"title":"Electronically tunable single FTFNTA-based universal memelement emulator using only grounded passive elements","authors":"","doi":"10.1016/j.vlsi.2024.102253","DOIUrl":"10.1016/j.vlsi.2024.102253","url":null,"abstract":"<div><p>An electronic circuit capable of performing the functions of all three memelements through simple configuration adjustments, known as a universal memelement emulator, addresses significant issues regarding the size and power consumption associated with integrated chips. This study aims to develop such a universal memelement emulator with configurable architecture requiring only few changes to switch into desired memelement emulator. The designed structure is based on only single active element known as the FTFNTA (Four Terminal Floating Nullor Transconductance Amplifier). The proposed circuit, in addition to a single FTFNTA, incorporates only four passive elements and three switches. Through the manipulation of these switches, the universal emulator can be configured to emulate three distinct memelements: flux-controlled memristor (FCMR), flux-controlled meminductor (FCMI), and charge-controlled memcapacitor (CCMC). The non-ideal analysis was conducted after considering the deviated parameters of the FTFNTA and associated parasitic elements and resultant behaviour is discussed. Simulation results conducted in the PSPICE environment validate the functionality of the realized memelements. Furthermore, verification of the concept is performed by implementing the FTFNTA-based circuit using commercially available ICs, specifically LM13700 and AD844, with the results discussed accordingly. The working of the realized memristor has also been verified by utilizing the proposed emulator (tuned as a memristor) in an associative learning circuit. Finally, the proposed emulator is validated experimentally using the physical ICs based breadboard implementation.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141963110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low dropout regulator design with 20.4 μA quiescent current and high power supply rejection 低压差稳压器设计，静态电流为 20.4 μA，电源抑制能力强

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-07-30 DOI: 10.1016/j.vlsi.2024.102242

引用次数: 0

An area efficient 64 point Radix-42 MDC FFT architecture for OFDM applications 适用于 OFDM 应用的 64 点 Radix-42 MDC FFT 高效面积架构

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-07-24 DOI: 10.1016/j.vlsi.2024.102244

引用次数: 0

Adaptive prairie dog optimization based variable length conditional counter for designing multiplier 用于设计乘法器的基于自适应草原犬优化的变长条件计数器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-07-22 DOI: 10.1016/j.vlsi.2024.102243

{"title":"Adaptive prairie dog optimization based variable length conditional counter for designing multiplier","authors":"","doi":"10.1016/j.vlsi.2024.102243","DOIUrl":"10.1016/j.vlsi.2024.102243","url":null,"abstract":"<div><p>Binary counters (BC) are electronic devices that are used for counting the particular events that have been happened, followed by storing and displaying the count numbers. BC includes clock signal with sequential logic circuit for the effectuation of counting operation. It is used in many applications like FM decoders to memory chips. In this work we designed a serial multiplier using the proposed Adaptive Prairie Dog optimization (APDO) based variable length conditional counter (VLCC) for the mitigation delay. The suggested work is motivated by the need for an efficient multiplier design to mitigate delay. Mitigating delay in multiplier design is essential for various reasons, particularly in the fields of digital signal processing, computer arithmetic, and high-performance computing. The proposed technique is used to design the multiplier with reduced path delay and enhances the slack interval with various frequencies. The maximized frequency operation is evaluated with the slack interval of the circuit. Simulations are made using Mentor Graphics EDA simulator tool and analyzed the slack time and compared with state-of-art works. The implementation of 8-bit binary multiplier is effectuated in CMOS technology. Our proposed design surpasses all the other design in terms of mitigated computational delay and enhanced slack time. At higher frequency, the proposed method offers improved slack time of 14 % and 68 % of multiplier circuit to reduce delay. Due to the simulation investigations, 18 % slack time improved and reduce 87 % to the critical path delay when compare 45 nm with the 350-nm CMOS technology.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141843812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-performance power spectral/bispectral estimator for biomedical signal processing applications using novel memory-based FFT processor 利用基于内存的新型 FFT 处理器为生物医学信号处理应用提供高性能功率谱/双谱估计器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-07-20 DOI: 10.1016/j.vlsi.2024.102241

{"title":"High-performance power spectral/bispectral estimator for biomedical signal processing applications using novel memory-based FFT processor","authors":"","doi":"10.1016/j.vlsi.2024.102241","DOIUrl":"10.1016/j.vlsi.2024.102241","url":null,"abstract":"<div><p>This research paper proposes a novel robust high-performance power spectrum estimator, and bispactral power density analyzer that has outstanding capabilities in estimating noisy biomedical signal's power spectrum, and bispectrum. Biomedical signals usually are exposed to several sources of noises such as electrical noise from environmental noise from external sources, electrical equipment, and biological noise from the body. Therefore, accuracy and reliability are the most important feature of these systems in processing non-stationary biomedical signals. The proposed computationally-efficient architecture is based on a radix-8 memory-based 1024-point Blackman-Tuckey method power spectral density (PSD) estimator. The proposed nonparametric estimator uses a novel shared-resource CORDIC-Ⅱ unit to avoid multiplications in FFT computation, as well as filtering operations implemented in folded architectures. In order to merge two FFTs, the module uses bidirectional fractional delay filters to estimate half delay samples. By using modified safe-scaling, valid final output would be achieved, without any averaging operation. The proposed and competing designs are implemented on Artix-7 FPGA which is an ideal option for DSP applications. As final results demonstrate, the hardware has a remarkable capability in operating in short word-lengths which allows high-performance in low-power applications to compute the power spectrum and bicoherence of a vital signal.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141841958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and implementation of deep learning-based object detection and tracking system 基于深度学习的物体检测与跟踪系统的设计与实现

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-07-17 DOI: 10.1016/j.vlsi.2024.102240

引用次数: 0

High-performance anti-series diode ring amplifier for switched capacitor circuits 用于开关电容器电路的高性能反串二极管环形放大器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-07-08 DOI: 10.1016/j.vlsi.2024.102236

Anmol Verma, Shubhang Srivastava, Shivam Bhardwaj, Ambika Prasad Shah

引用次数: 0