Integration-The Vlsi Journal最新文献_第3页

Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability 在 RISC-V 处理器微体系结构中集成纠错和检测技术以提高可靠性

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-12 DOI: 10.1016/j.vlsi.2024.102282

Aswin Sreekumar, Bolupadra Sai Shankar, B. Naresh Kumar Reddy

{"title":"Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability","authors":"Aswin Sreekumar, Bolupadra Sai Shankar, B. Naresh Kumar Reddy","doi":"10.1016/j.vlsi.2024.102282","DOIUrl":"10.1016/j.vlsi.2024.102282","url":null,"abstract":"<div><p>An essential consideration in processor design is ensuring reliability, particularly in demanding environments such as outer space and nuclear plants. To mitigate the effects of errors and enable error recovery, processors need to incorporate fault tolerance techniques. One common type of error is SEU (Single Event Upset), which affects various microelectronic devices including microprocessors, microcontrollers, and semiconductor memory devices. While error mitigation techniques have been developed for processors based on architectures like ARM (Advanced RISC Machine) and MIPS (Million Instructions Per Second), there is a gap in research for open-source ISAs (Instruction Set Architecture) like RISC-V, which this paper aims to address. This paper focuses on designing a fault-tolerant microarchitecture for a RISC-V processor that can correct one-bit errors, detect up to two-bit errors, and integrate lockstep and pipeline rollback features at a lower LUTs (Look Up Tables) consumption by re-using the same hardware pipeline for error mitigation and recovery through instruction mimicking. By incorporating these features, the proposed approach enhances the system’s fault tolerance by detecting and correcting errors caused by transient events and achieves a lower effective die size upon realization compared to contemporary works. The proposed microarchitecture design was simulated and synthesized using the Vivado Design Suite 2023.1 and implemented on a Zynq 7000 SoC ZC702 Evaluation Kit.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142242434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A general and accurate pattern search method for various scenarios 适用于各种情况的通用精确模式搜索法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-11 DOI: 10.1016/j.vlsi.2024.102281

Congyi Zhang , Xu He , Hao Sang , Hengzhou Yuan , Dawei Liu , Yang Guo

引用次数: 0

Synchronous control of memristive hindmarsh-rose neuron models with extreme multistability 具有极端多稳定性的记忆性后马什-蔷薇神经元模型的同步控制

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-10 DOI: 10.1016/j.vlsi.2024.102280

Shaohui Yan, Jialong Wang, Jincai Song

引用次数: 0

Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB 两阶段有序逃逸路由与 LP 和启发式算法相结合，用于大型印刷电路板

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-07 DOI: 10.1016/j.vlsi.2024.102270

Disi Lin , Chuandong Chen , Rongshan Wei , Qinghai Liu , Huan He , Ziran Zhu , Zhifeng Lin , Jianli Chen

{"title":"Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB","authors":"Disi Lin , Chuandong Chen , Rongshan Wei , Qinghai Liu , Huan He , Ziran Zhu , Zhifeng Lin , Jianli Chen","doi":"10.1016/j.vlsi.2024.102270","DOIUrl":"10.1016/j.vlsi.2024.102270","url":null,"abstract":"<div><div>The Ordered Escape Routing (OER) problem, which is an NP-hard problem, is critical to PCB design. Primary methods based on integer linear programming (ILP) work well on small-scale PCBs with fewer pins. However, when dealing with large-scale instances, traditional ILP strategies frequently cause time violations as the number of variables increases due to time-consuming preprocessing. In addition, heuristic algorithms have a time advantage when dealing with specific problems. In this paper, We propose an efficient two-stage escape routing method that employs LP for global routing and uses a heuristic algorithm to deal with the path intersection problem to minimize wiring length and runtime for large-scale PCBs. We first model the OER problem as a min-cost multi-commodity flow problem and use ILP to solve it. Then, we relax the non-crossing constraints and transform the ILP model into an LP model to reduce the runtime. we also construct a crossing graph according to the intersection of routing paths and propose a heuristic algorithm to locate congestion quickly. Finally, we reduce the local area capacity and allow global automatic congestion optimization. Compared with the state-of-the-art work, experimental results show that our method can reduce the routing time by 60% and handle larger-scale PCB escape routing problems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142323992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A wide-output buck DC-DC power management IC 宽输出降压型 DC-DC 电源管理集成电路

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-06 DOI: 10.1016/j.vlsi.2024.102278

Xinglong Guo , Qingqing Wu , Yanhang Du , Xinyu Li , Zihao Cui

{"title":"A wide-output buck DC-DC power management IC","authors":"Xinglong Guo , Qingqing Wu , Yanhang Du , Xinyu Li , Zihao Cui","doi":"10.1016/j.vlsi.2024.102278","DOIUrl":"10.1016/j.vlsi.2024.102278","url":null,"abstract":"<div><p>-This article designs and develops a wide-input voltage, high-efficiency, small-size, and peak current-mode control step-down DC-DC converter. The Cadence Spectre simulation tool is used for system simulation to verify the performance of the chip. The overall research content of the article includes the function of the output under heavy load, light load and the stability of the output under transient load changes. The specific content of the research is buck synchronous step-down DC-DC converter chip with pulse modulated. It is provided with an input-voltage range of 6 V–80 V and maximum output-voltage range 72 V. The chip possesses wide operating temperature range of −20 °C to 130 °C. The 92 % high-efficiency can be achieved by using a PWM/PFM hybrid modulation method. When achieving transient load jump, the output voltage change shall not exceed 150 mV. The maximum load current of the chip is 1 A. Furthermore, the chip is packaged and samples can be obtained, and the output light load/heavy load, and other functions are tested through the circuit board. In addition, the chip achieved tape out by using 0.18 μm CMOS process with size of 2027 μm <span><math><mrow><mo>×</mo></mrow></math></span> 2020 μm. The converter features current mode control to simplify external compensation and optimize transient response through a wide range of inductors and output capacitors. It can be adopted user-programmable soft-start time to prevent inrush current during startup. It also includes thermal shutdown protection to provide safe and smooth operation in operating conditions.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142164178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

LA-ring based non-linear components: Application to image security 基于 LA 环的非线性组件：图像安全应用

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-05 DOI: 10.1016/j.vlsi.2024.102279

Nazli Sanam, Summiya Mumtaz, Samreen Khalid

{"title":"LA-ring based non-linear components: Application to image security","authors":"Nazli Sanam, Summiya Mumtaz, Samreen Khalid","doi":"10.1016/j.vlsi.2024.102279","DOIUrl":"10.1016/j.vlsi.2024.102279","url":null,"abstract":"<div><p>The prevalent utilization of symmetric block ciphers in contemporary information security systems reinforces the need for immediate action to increase their effectiveness. This task is considered crucial in the synthesis of high-quality cryptographic primitives, particularly S-boxes. In accordance with this requirement, the current article demonstrates a strategy for generating an 8 × 8 S-box drawing over an LA-ring of order 1024, which is considered a substantial class of non-associative rings. For the purpose of investigating LA-ring and their practical uses, it is essential to have illustrative examples. However, obtaining such examples using current methods is tedious and yields limited results. Therefore, this research explores an intriguing opportunity for an extensive exploration of LA-ring, far exceeding the limitations previously established and offering a valuable analytical approach for creating examples of higher-order LA-ring by drawing upon lower orders. The manuscript also performs a variety of standard evaluation tests based on five core indicators, which highlight their potential as parallels to the existing frameworks. By using the crafted S-box, an image encryption approach is launched that aims to enhance security measures. It is therefore seen that the recommended S-box has shown a high potential for causing confusion during the substitution phase, and a 3D chaotic map is implemented for the pixel permutation in order to create diffusion into the colour image. Certainly, the discovery is leading to a foundational framework among academics and is expected to serve as the basis for numerous implementations in the future.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142242433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 3D-stack DRAM-based PNM architecture design 基于 3D 堆栈 DRAM 的 PNM 架构设计

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-02 DOI: 10.1016/j.vlsi.2024.102266

Qiang Zhou , Bing Wang , XinTing Xiao

引用次数: 0

Integrated electrical silicon interconnects for short-range high-speed millimeter-wave and terahertz communications 用于短程高速毫米波和太赫兹通信的集成电子硅互连器件

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-31 DOI: 10.1016/j.vlsi.2024.102267

Zhihong Lin , Shiqi Chen , Yuan Liang , Lin Peng

{"title":"Integrated electrical silicon interconnects for short-range high-speed millimeter-wave and terahertz communications","authors":"Zhihong Lin , Shiqi Chen , Yuan Liang , Lin Peng","doi":"10.1016/j.vlsi.2024.102267","DOIUrl":"10.1016/j.vlsi.2024.102267","url":null,"abstract":"<div><p>—Millimeter-wave and terahertz interconnects implemented in advanced complementary metal oxide semiconductor (CMOS) technologies have emerged as promising solutions to fix the issues encountered by baseband interconnects and optical interconnects across specific communication ranges. Over the last decade, significant attempts to advance millimeter-wave and terahertz electronics and platforms have been made. Notably, there have been ground-breaking advancements in active components, including modulation techniques, low-noise receivers, efficient and high-output-power signal generators, and high-frequency clock synthesizers. Nevertheless, since energy efficiency is of paramount importance for interconnect applications, it is necessary to prioritize efficiency enhancements over improvements in signal power, signal integrity and noise related performance. Strategies to improve system output power and phase noise as well as strategies to reduce channel loss and channel electromagnetic crosstalk should leverage alternative approaches, such as architectural optimizations and array configurations, rather than prioritizing energy efficiency. As such, the progression of passive channel technology is equally vital. While reducing channel insertion loss is essential for extending communication reach, channel dispersion and crosstalk limitations at the interface level present critical challenges to achieving optimal bandwidth over distances of up to a few meters. This underscores the need for a balanced focus on both active and passive component innovations to fully harness the potential of millimeter-wave and terahertz interconnects in overcoming the limitations of current CMOS technologies.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142228524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An analytical placement algorithm with looking-ahead routing topology optimization 具有前瞻性路由拓扑优化功能的分析放置算法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-31 DOI: 10.1016/j.vlsi.2024.102264

Min Wei , Xingyu Tong , Zhijie Cai , Peng Zou , Zhifeng Lin , Jianli Chen

{"title":"An analytical placement algorithm with looking-ahead routing topology optimization","authors":"Min Wei , Xingyu Tong , Zhijie Cai , Peng Zou , Zhifeng Lin , Jianli Chen","doi":"10.1016/j.vlsi.2024.102264","DOIUrl":"10.1016/j.vlsi.2024.102264","url":null,"abstract":"<div><p>Placement is a critical step in the modern VLSI design flow, as it dramatically determines the performance of circuit designs. Most placement algorithms estimate the design performance with a half-perimeter wirelength (HPWL) and target it as their optimization objective. The wirelength model used by these algorithms limits their ability to optimize the internal routing topology, which can lead to discrepancies between estimates and the actual routing wirelength. This paper proposes an analytical placement algorithm to optimize the internal routing topology. We first introduce a differential wirelength model in the global placement stage based on an ideal routing topology RSMT. Through screening and tracing various segments, this model can generate meaningful gradients for interior points during gradient computation. Then, after global placement, we propose a cell refinement algorithm and further optimize the routing wirelength with swift density control. Experiments on ICCAD2015 benchmarks show that our algorithm can achieve a 3% improvement in routing wirelength, 0.8% in HPWL, and 23.8% in TNS compared with the state-of-the-art analytical placer. On industrial benchmarks, our algorithm can also achieve a 10.6% improvement in routing wirelength, 27.3% in WNS, and 34.4% in TNS.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142150576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A three-stage single-miller CMOS OTA with no lower load capacitor limit 无负载电容下限的三级单填充 CMOS OTA

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-30 DOI: 10.1016/j.vlsi.2024.102269

P. Manikandan

引用次数: 0