Integration-The Vlsi Journal最新文献_第3页

Observability in systems with extreme multistability 极端多稳定系统的可观测性

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-04-04 DOI: 10.1016/j.vlsi.2025.102412

J.M. Rodríguez-Ornelas , R. Sevilla-Escoboza , Onofre Orozco-López , R.R. Rivera-Durón , V.P. Vera-Ávila

{"title":"Observability in systems with extreme multistability","authors":"J.M. Rodríguez-Ornelas , R. Sevilla-Escoboza , Onofre Orozco-López , R.R. Rivera-Durón , V.P. Vera-Ávila","doi":"10.1016/j.vlsi.2025.102412","DOIUrl":"10.1016/j.vlsi.2025.102412","url":null,"abstract":"<div><div>In control engineering and dynamical systems, obtaining accurate measurements of a system’s state vector can be challenging due to the inaccessibility of certain internal states or the prohibitive cost of measurement. To address these issues, observers are employed to reconstruct the system’s state. While linear observers have proven effective for linear systems, applying them to nonlinear systems presents additional challenges and opportunities. In this paper, we explored the design and implementation of a linear observer applied on a 6-variable dynamical system, namely extreme multistable Rössler system (EMRS). Our proposed methodology leverages observability indices and graphical representations to enhance the linearization process at points of maximum observability. This approach allows for generating the gain set for a Luenberger observer, thereby improving its performance in estimating the states of a complex nonlinear system such as the EMRS. Our numerical and experimental results demonstrate the effectiveness of linearization using observability coefficients for the design of a linear observer. This observer can efficiently track and reconstruct the dynamics of a multi-stable nonlinear system, enabling the use of a linear observer on a nonlinear system.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102412"},"PeriodicalIF":2.2,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143768410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel low-hardware-cost scan chain architecture resilient to scanSAT attack 一种新型的低硬件成本扫描链结构，可抵御扫描卫星攻击

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-04-01 DOI: 10.1016/j.vlsi.2025.102414

Fatih Tiryakioğlu , Ahmet Unutulmaz , İhsan Çiçek , Ali Tangel

引用次数: 0

A 28-GHz highly efficient Class-J SiGe power amplifier with pi-type load network 具有pi型负载网络的28 ghz高效j类SiGe功率放大器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-25 DOI: 10.1016/j.vlsi.2025.102415

Vasileios Manouras, Yannis Papananos

引用次数: 0

Analysis of false lock in Mueller-Muller clock and data recovery system Mueller-Muller时钟及数据恢复系统中的假锁分析

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-24 DOI: 10.1016/j.vlsi.2025.102413

Yahao Fang , Deng Luo , Bin Liang , Jianjun Chen , Yaqing Chi , Hanhan Sun , Qian Sun , Jingtian Liu

{"title":"Analysis of false lock in Mueller-Muller clock and data recovery system","authors":"Yahao Fang , Deng Luo , Bin Liang , Jianjun Chen , Yaqing Chi , Hanhan Sun , Qian Sun , Jingtian Liu","doi":"10.1016/j.vlsi.2025.102413","DOIUrl":"10.1016/j.vlsi.2025.102413","url":null,"abstract":"<div><div>As serializer/deserializer (SerDes) architectures evolve to support multi-Gbps data rates, Four-level Pulse Amplitude Modulation (PAM4) has emerged as the dominant signaling scheme owing to its superior spectral efficiency. However, the conventional Mueller-Muller Clock and Data Recovery (MMCDR) architecture exhibits critical false lock artifacts when processing PAM4 signals, leading to significant degradation in Jitter Tolerance (JTOL) and Bit Error Rate (BER). Through theoretical analysis, we demonstrate that the root cause lies in the misalignment between the sampled signal and decision values during phase detection. To address this limitation, we introduce a novel Phase Detector (PD) architecture. A comprehensive CDR behavioral model integrating the proposed PD is developed in Simulink. Simulation results demonstrate that the improved PD avoids false lock compared to conventional MMPD implementations. Furthermore, the proposed PD achieves superior jitter tolerance performance. These advancements provide a hardware-efficient and readily implementable solution for high-speed PAM4 SerDes systems operating in lossy channels.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102413"},"PeriodicalIF":2.2,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143716156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Heuristic approaches to energy optimization in deep submicron bus design through QAP formulation 基于QAP公式的深亚微米总线设计能量优化启发式方法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-20 DOI: 10.1016/j.vlsi.2025.102404

Konstantinos Papalamprou

引用次数: 0

Spherical chaotic trajectory tracking and formation of unmanned aerial vehicles in master–slave configuration with intermediary system 带有中介系统的主从构型无人机球面混沌轨迹跟踪与形成

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-19 DOI: 10.1016/j.vlsi.2025.102405

A. Durán-Covarrubias , A. Arellano-Delgado , C. Cruz-Hernández , J.J. Cetina-Denis , R.M. López-Gutiérrez

引用次数: 0

High-Precision Spatial Filtering with AI-driven control and multicolor laser testing for interferometric application 高精度空间滤波与人工智能驱动控制和多色激光测试干涉应用

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-19 DOI: 10.1016/j.vlsi.2025.102406

Gregorio A. Oropeza-Gomez, J. Onofre Orozco-López, Francisco J. Casillas-Rodríguez, Francisco G. Peña-Lecona, Jesus Muñoz-Maciel, Miguel Mora-Gonzalez

{"title":"High-Precision Spatial Filtering with AI-driven control and multicolor laser testing for interferometric application","authors":"Gregorio A. Oropeza-Gomez, J. Onofre Orozco-López, Francisco J. Casillas-Rodríguez, Francisco G. Peña-Lecona, Jesus Muñoz-Maciel, Miguel Mora-Gonzalez","doi":"10.1016/j.vlsi.2025.102406","DOIUrl":"10.1016/j.vlsi.2025.102406","url":null,"abstract":"<div><div>This study presents a novel automated spatial filtering system designed for high-precision alignment and operation across multiple laser wavelengths. Spatial filtering has been a cornerstone of optical research and applications, playing a critical role in beam quality improvement, noise reduction, and the mitigation of back reflections. Building upon the advancements in pinhole designs, external-cavity configurations, and beam alignment methods, our system integrates a laser diode, a <span><math><mrow><mn>10</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> pinhole, servomotors for micrometric adjustments, and a CCD camera for real-time feedback. Robust testing was conducted with red, green, and blue lasers (635, 520, and 405 nm) to ensure consistent performance across varying wavelengths. The control mechanism employs a two-stage approach: coarse alignment using a back-propagation artificial neural network for efficient displacement estimation, followed by fine-tuning with an enhanced proportional–integral–derivative (PID) controller to achieve sub-micrometric precision. This hybrid approach addresses the limitations of traditional manual methods and standalone controllers, significantly reducing alignment time and improving accuracy. The software architecture, implemented in Python, LabVIEW, and MySQL, ensures cross-platform compatibility and modular integration into embedded systems. This automated solution is particularly suitable for holographic and interferometric experiments that demand continuous and precise spatial filtering. By achieving high reproducibility and adaptability across multiple wavelengths, this advancement offers a scalable and reliable solution to enhance experimental precision in optical research and engineering applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102406"},"PeriodicalIF":2.2,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143678963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel locally active memristive autapse-coupled Hopfield neural network under electromagnetic radiation 电磁辐射下一种新的局部有源忆阻autapase耦合Hopfield神经网络

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-19 DOI: 10.1016/j.vlsi.2025.102410

Qiuzhen Wan , Simiao Chen , Tieqiao Liu , Haixiang Lan , Kun Shen

{"title":"A novel locally active memristive autapse-coupled Hopfield neural network under electromagnetic radiation","authors":"Qiuzhen Wan , Simiao Chen , Tieqiao Liu , Haixiang Lan , Kun Shen","doi":"10.1016/j.vlsi.2025.102410","DOIUrl":"10.1016/j.vlsi.2025.102410","url":null,"abstract":"<div><div>In this paper, a memristive Hopfield neural network (HNN) model in complex electromagnetic environment is established by introducing a novel locally active memristor as a connected autapse in neural network, where the effect of electromagnetic radiation is described by a quadratic nonlinear memristor. The non-volatile and locally active characteristics of the proposed locally active memristor are demonstrated by the power-off curve and DC <em>V</em>-<em>I</em> plot respectively. With the autapse connection weight and electromagnetic radiation considered,the memristive HNN model is investigated in detail by theoretical and numerical analysis. Compared with the other neural networks, the abundant dynamics can be observed in the proposed memristive HNN model when the appropriate system parameters are chosen, including stable points, periodic attractors, chaotic attractors, period doubling bifurcation, chaos crisis, coexistence multiple attractors, and so on. Besides, an analog circuit on PSIM and a digital hardware platform on FPGA are implemented to confirm the feasibility of the memristive HNN model and the experimental results are highly consistent with the numerical ones.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102410"},"PeriodicalIF":2.2,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143678990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimizing value prediction for ILP processors: A design space exploration approach 优化值预测的ILP处理器：设计空间探索方法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-17 DOI: 10.1016/j.vlsi.2025.102402

Ling Yang, Zhong Zheng, Libo Huang, Run Yan, Sheng Ma, Yongwen Wang, Weixia Xu

{"title":"Optimizing value prediction for ILP processors: A design space exploration approach","authors":"Ling Yang, Zhong Zheng, Libo Huang, Run Yan, Sheng Ma, Yongwen Wang, Weixia Xu","doi":"10.1016/j.vlsi.2025.102402","DOIUrl":"10.1016/j.vlsi.2025.102402","url":null,"abstract":"<div><div>Value prediction is a microarchitectural technique that enhances processor performance by speculatively breaking true data dependencies. It has demonstrated improved performance in both single-threaded and multi-threaded workloads, rendering it an appealing microarchitectural approach. While high-performance value predictors can achieve impressive accuracy, they may also incur significant costs in terms of area, power consumption, and complexity. Therefore, there is a demand for lightweight value prediction techniques capable of striking a favorable balance between performance and overhead. However, designing value predictors with superior performance using limited resources presents an urgent challenge, as inappropriate parameter configurations may result in cost overruns and degraded processor performance. Consequently, this work proposes a design space exploration framework for the state-of-the-art EVES value predictor, aiming to efficiently configure the design parameters of the value predictor within constrained RAM resources. Additionally, the article evaluates the performance of the explored value predictor across a wide range of workloads. The explored value predictors exhibit high efficiency across RAM sizes ranging from 2KB to 16KB while maintaining acceptable computational complexity. Furthermore, the results indicate that the explored value predictor achieves optimal efficiency under the 2KB constraint, with the highest acceleration-to-cost ratio reaching 8.74% per KB, approximately three times greater than that of the current state-of-the-art value predictor.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102402"},"PeriodicalIF":2.2,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143644357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A neuromorphic hardware architecture based on TTFS coding with temporal quantization for spiking neural networks 一种基于时间量化的脉冲神经网络TTFS编码的神经形态硬件结构

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-17 DOI: 10.1016/j.vlsi.2025.102403

Yuxuan Yang , Qihu Xie , Zihao Xuan , Song Chen , Yi Kang

{"title":"A neuromorphic hardware architecture based on TTFS coding with temporal quantization for spiking neural networks","authors":"Yuxuan Yang , Qihu Xie , Zihao Xuan , Song Chen , Yi Kang","doi":"10.1016/j.vlsi.2025.102403","DOIUrl":"10.1016/j.vlsi.2025.102403","url":null,"abstract":"<div><div>In recent years, spiking neural networks (SNNs) have gained significant attention due to their biologically realistic and event-driven properties. Time-to-First-Spike (TTFS) coding is a coding scheme for SNNs where neurons are fired only once throughout the inference process, reducing the number of spikes and improving energy efficiency. However, the SNNs with TTFS coding have an issue of low classification accuracy. This paper first introduces TQ-TTFS, a temporal quantization on the TTFS neuron model to address this issue. TQ-TTFS significantly alleviates overfitting caused by early firing and improves the classification accuracy of SNNs. Based on TQ-TTFS, we design a hardware architecture with a new inference scheme called Hybrid Priority Inference (HPI) which greatly reduces the frequency of weight access and supports temporal parallel computation. To further decrease storage overhead, we also introduce shared storage and membrane potential quantization. The proposed temporal quantization neuron model and hardware architecture demonstrate excellent performance. Our simulations show that TQ-TTFS achieves classification accuracy of 98.6% on the MNIST dataset, 90.2% on the FashionMNIST dataset, and 80.54% on the CIFAR-10 dataset, which are better than SOTA among temporal coded SNNs. Our FPGA implementation of the proposed hardware architecture has inference time of only 4.4 <span><math><mi>μ</mi></math></span>s per image on the MNIST dataset and 24 <span><math><mi>μ</mi></math></span>s per image on the FashionMNIST dataset. The energy consumption for these inferences is only 4 <span><math><mi>μ</mi></math></span>J and 32 <span><math><mi>μ</mi></math></span>J, respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102403"},"PeriodicalIF":2.2,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143678987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0