Integration-The Vlsi Journal最新文献_第3页

A random modular-reduction (RMR)-based ASIC design of CRYSTALS-Kyber engine against side-channel attacks 基于随机模减少（RMR）的CRYSTALS-Kyber引擎抗侧信道攻击的ASIC设计

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2026-05-01 Epub Date: 2026-02-07 DOI: 10.1016/j.vlsi.2026.102680

Jinghe Wang , Zhiyuan Pan , Nengyuan Sun , Zhaoyi Niu , Wenrui Liu , Jiafeng Cheng , Kai Shi , Jianghong Li , Jiaqi Wang , Jiawei Zhang , Linhan Wang , Kangning Song , Yuzhu Wu , Weize Yu

{"title":"A random modular-reduction (RMR)-based ASIC design of CRYSTALS-Kyber engine against side-channel attacks","authors":"Jinghe Wang , Zhiyuan Pan , Nengyuan Sun , Zhaoyi Niu , Wenrui Liu , Jiafeng Cheng , Kai Shi , Jianghong Li , Jiaqi Wang , Jiawei Zhang , Linhan Wang , Kangning Song , Yuzhu Wu , Weize Yu","doi":"10.1016/j.vlsi.2026.102680","DOIUrl":"10.1016/j.vlsi.2026.102680","url":null,"abstract":"<div><div>In this paper, a high-performance application-specific integrated circuit (ASIC) design of CRYSTALS-Kyber is proposed for accelerating post-quantum cryptography (PQC) applications. Unlike a regular Barrett modular-reduction (BMR) that includes only a single modulus, two different moduli are utilized in the new BMR architecture for accelerating the number-theoretic transform (NTT) module within the Kyber algorithm. To protect against side-channel attacks (SCAs), the two moduli within the proposed BMR are randomized to introduce uncertainty in the power profile of the Kyber algorithm. In addition, in order to acquire the optimum power/area/performance/security trade-off values for the proposed CRYSTALS-Kyber, novel convex optimization models are established to investigate the impact of random modulus distributions on the overall ASIC design. As shown in the results, the proposed random modular-reduction (RMR)-based Kyber engine is capable of achieving a <span><math><mrow><mn>92</mn><mo>.</mo><mn>65</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span> performance (an area of 1.63 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>) with a minimum measurement-to-disclosure (MTD) enhancement of 454.5x against 1st-order SCAs, under the synthesis of SMIC 55 nm process design kits (PDK).</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102680"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Identifying malicious modules using deformable graph convolutional network-based security framework for reliable VLSI circuit protection 利用基于可变形图卷积网络的安全框架识别恶意模块，实现可靠的VLSI电路保护

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2026-05-01 Epub Date: 2025-12-15 DOI: 10.1016/j.vlsi.2025.102633

M. Maria Rubiston , B.R. Tapas Bapu

{"title":"Identifying malicious modules using deformable graph convolutional network-based security framework for reliable VLSI circuit protection","authors":"M. Maria Rubiston , B.R. Tapas Bapu","doi":"10.1016/j.vlsi.2025.102633","DOIUrl":"10.1016/j.vlsi.2025.102633","url":null,"abstract":"<div><div>Hardware security remains a significant concern because Very Large Scale Integration (VLSI) circuits have become increasingly complex, and industries have begun utilizing untrusted third-party Intellectual Property. Security threats from Hardware Trojans (HTs) remain particularly dangerous since these devices create unethical modifications that break circuit integrity while challenging reliability and damaging confidentiality. Current HT detection methods struggle to scale properly and maintain high accuracy rates due to malicious Trojan design strategies, as well as the constraints of functional testing, side-channel evaluation, and formal verification techniques. To address these challenges, this research introduces DGCoNet-GBOA, a Diffusion Kernel Attention Network with Deformable Graph Convolutional Network-Based Security Framework optimized using the Gooseneck Barnacle Optimization Algorithm (GBOA) for real-time and highly accurate HT detection. The proposed framework extracts structural, power, and transition probability features using Scale-aware Modulation Meet Transformer (S-ammT) and balances the dataset using Diminishing Batch Normalization (DimBN). The DGCoNet framework analyses gate-level netlists (GLNs) as graphical networks to identify HT development changes, and GBOA uses optimization methods that boost detection precision capabilities. The model displays precise Trojan detection abilities, achieving 99.87 % accuracy with just 0.12 % false positive occurrences and 99.91 % precision when testing ISCAS'85 and ISCAS'89 benchmark systems. The proposed DGCoNet-GBOA method achieves an average 0.7–4.5 % improvement in accuracy over existing state-of-the-art approaches across ISCAS'85 and ISCAS'89 benchmarks. The framework built in this research provides scalable, high-reliability HT detection capabilities to safeguard VLSI circuits from present-day hardware security threats during semiconductor design.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102633"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-performance FIR filter designs using Brent Kung Adder and pipelined Vedic multiplier 高性能FIR滤波器设计使用布伦特孔加法器和流水线吠陀乘法器

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2026-05-01 Epub Date: 2026-01-03 DOI: 10.1016/j.vlsi.2025.102645

J. Banumathi, G. Karthy

{"title":"High-performance FIR filter designs using Brent Kung Adder and pipelined Vedic multiplier","authors":"J. Banumathi, G. Karthy","doi":"10.1016/j.vlsi.2025.102645","DOIUrl":"10.1016/j.vlsi.2025.102645","url":null,"abstract":"<div><div>Signal processing widely uses Finite Impulse Response (FIR) filters because of their stability and linear phase. However, traditional FIR filter designs are limited by multiplication operations that lead to high hardware utilization and delay. To address this, modified FIR filters with optimized multipliers and adders are being developed to improve hardware resource utilization and delay performance. This paper presents novel designs for 8-tap and 16-tap FIR filters, leveraging Brent-Kung Adders (BKA) and Pipelined (P) Urdhva Triyakbhyam Vedic multipliers (UTVM) to achieve minimal delay and enhanced performance. Three architectures—Pipelined FIR using UTVM with BKA (PFIR-UTVM-BKA), FIR using PUTVM with BKA (FIR-PUTVM-BKA), and Pipelined FIR using PUTVM with BKA (PFIR-PUTVM-BKA)—were implemented with different device specifications on Kintex-7, Virtex-7, and Zynq 7000 platforms using Xilinx Vivado 2022.2 and ASIC 45 nm, simulated in Verilog. In FPGA, the proposed multiplier reduces delay by 43 %, 61.55 %, 73.01 %, and 78.51 % across different bit widths, and power, delay, and (power delay Product) PDP were reduced by 82.16 %,94.34 % and 98.99 % respectively, in ASIC. Additionally, the proposed FIR filter architectures achieve significant improvements, including 51.88 % and 27.13 % delay reduction, 75.40 % slice improvement, and 92.53 % and 97.03 % enhancement in slice registers for 8-tap and 16-tap 8-bit designs in FPGA, and power, delay, and PDP (Power Delay Product) were reduced by 87.97 %,97.59 % and 99.71 % respectively, in ASIC. These advancements make the proposed FIR filters highly suitable for high-speed digital signal processing (DSP) applications, where efficient processing and minimized latency are crucial. Integrating PVM and BKA plays a pivotal role in achieving these performance enhancements, positioning these filter designs as promising solutions for next-generation signal processing systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102645"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhanced security for static random access memory with armadillo Catboost 增强安全的静态随机存取存储器与犰狳Catboost

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2026-05-01 Epub Date: 2026-01-29 DOI: 10.1016/j.vlsi.2026.102672

K.I. RaviKumar , K. Anusha , C. Kalal Vijayalaxmi , T. Kshitija , M. Ayesha Siddiqa Khanum

{"title":"Enhanced security for static random access memory with armadillo Catboost","authors":"K.I. RaviKumar , K. Anusha , C. Kalal Vijayalaxmi , T. Kshitija , M. Ayesha Siddiqa Khanum","doi":"10.1016/j.vlsi.2026.102672","DOIUrl":"10.1016/j.vlsi.2026.102672","url":null,"abstract":"<div><div>Very Large Scale Integration (VLSI) design has become a critical aspect of high-speed chip communications due to its simple, efficient register and data access, but these systems can be vulnerable to security attacks, leading to excessive traffic and slow performance. Therefore, the SRAM control unit uses a novel Armadillo Catboost Security Control (ACSC) design. First, an SRAM block was built with the controller's associated facilities. Then, the ACSC design was created using the Armadillo fitness traits, with the addition of CatBoost machine learning capabilities to mitigate threats. When many users are communicating within a large dataset, the ACSC protects the system from vulnerabilities. Key performance indicators are assessed and compared with existing systems, including processing time, secrecy score, memory usage, traffic rate, power consumption, delay, and bit error rate (BER). The developed model is validated using several metrics, and it achieves a power consumption of 2.98 mW, a memory usage of 7446.96 MB, a BER of 0.00276 %, a delay of 1.97 ns, a confidentiality score of 95 %, and a processing time of 59.21s. This model has superior performance, security, and operational performance compared to existing systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102672"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MTJ-back-gate SRAM CIM with replica quantization for temperature robust 具有副本量化的mtj -后门SRAM CIM具有温度鲁棒性

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2026-05-01 Epub Date: 2026-02-10 DOI: 10.1016/j.vlsi.2026.102682

Yongliang Zhou, Chengxing Dai, Yufei He, Xiulong Wu, Chunyu Peng

引用次数: 0

A test data compression method based on sliding-window encoding and matching length reuse 一种基于滑动窗口编码和匹配长度复用的测试数据压缩方法

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2026-05-01 Epub Date: 2026-01-12 DOI: 10.1016/j.vlsi.2026.102663

Yuanfa Ji , Haihui Zhang , Xiyan Sun , Furong Jiang , Qiang Fu

{"title":"A test data compression method based on sliding-window encoding and matching length reuse","authors":"Yuanfa Ji , Haihui Zhang , Xiyan Sun , Furong Jiang , Qiang Fu","doi":"10.1016/j.vlsi.2026.102663","DOIUrl":"10.1016/j.vlsi.2026.102663","url":null,"abstract":"<div><div>With the continuous increase in chip integration density and reliability requirements, test data volume has grown significantly. At the same time, limitations of automatic test equipment in terms of physical I/O channel count, memory capacity, and data transmission bandwidth have further raised test costs. To address these challenges, this paper proposes a test data compression method based on sliding-window encoding. This approach identifies repeated sequences in the data to be encoded and replaces them with shorter codewords, thereby achieving effective compression. Furthermore, a match length reuse mechanism is introduced, which considerably enhances both codeword utilization efficiency and compression performance. Additionally, this paper systematically analyzes the impact of encoding parameters on the compression ratio, optimizes the encoding scheme considering hardware overhead, and designs a corresponding decompression architecture. Experimental results show that the proposed method achieves an average compression ratio of 66.86% on ISCAS’89 benchmark circuits. This provides an innovative and practical solution for test data compression.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102663"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145980164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Non-equilibrium oscillator with a diode: Dynamics and application 带二极管的非平衡振荡器：动力学与应用

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2026-05-01 Epub Date: 2026-01-06 DOI: 10.1016/j.vlsi.2026.102653

Viet-Thanh Pham , Victor Kamdoum Tamba , Luigi Fortuna

引用次数: 0

Low-temperature-drift voltage reference design using magnetic tunnel junctions 采用磁隧道结的低温漂移电压参考设计

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2026-05-01 Epub Date: 2026-01-02 DOI: 10.1016/j.vlsi.2025.102644

Yongliang Zhou , Yingxue Sun , Beibei Zhang , Wangyong Si , Jingxue Zhong , Weizhe Tan , Chunyu Peng , Xiulong Wu

{"title":"Low-temperature-drift voltage reference design using magnetic tunnel junctions","authors":"Yongliang Zhou , Yingxue Sun , Beibei Zhang , Wangyong Si , Jingxue Zhong , Weizhe Tan , Chunyu Peng , Xiulong Wu","doi":"10.1016/j.vlsi.2025.102644","DOIUrl":"10.1016/j.vlsi.2025.102644","url":null,"abstract":"<div><div>This article primarily investigates the temperature characteristics of magnetic tunnel junctions (MTJ) and exploits their tunnel magneto-resistance (TMR) effect to compensate for temperature-induced mismatches arising from CMOS temperature variations. In this work, the beta-multiplier reference and Kuijk bandgap reference are simulated on the 28 nm node. The proposed designs achieve improvements in temperature stability while maintaining low-voltage operation. Specifically, the circuit was redesigned based on a beta-multiplier voltage-reference topology in which MTJs replace resistors, with the explicit aim of strengthening the negative-feedback loop. As a result, stable operation is achieved at a minimum supply voltage of 0.6 V over the temperature range 0 °C to 110 °C. The reference voltage exhibits a line sensitivity of 0.57%/V, a temperature coefficient of 35.2 ppm/°C, and a nominal output of 441.6 mV. Drawing on MTJ-based compensation techniques, the modified Kuijk bandgap reference replaces the BJT-based temperature-compensation element with an MTJ device, yielding a reference voltage with a line sensitivity of 0.096%/V, a temperature coefficient of 11.8 ppm/°C, and a nominal output of 1.65 V. Beyond the electrical benefits, the use of MTJs enables vertical integration of the compensating elements, delivering substantial area savings — approximately 50% reduction for the beta-multiplier implementation and about 66.5% for the modified bandgap — thereby producing a more compact and competitive solution for high-performance precision voltage references.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102644"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A method for mathematically synthesizing double-exponential signal generation on-the-fly on FPGA and its evaluation 一种基于FPGA的双指数信号生成数学合成方法及其评价

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2026-05-01 Epub Date: 2026-01-09 DOI: 10.1016/j.vlsi.2026.102661

Aydin Tarik Zengin

{"title":"A method for mathematically synthesizing double-exponential signal generation on-the-fly on FPGA and its evaluation","authors":"Aydin Tarik Zengin","doi":"10.1016/j.vlsi.2026.102661","DOIUrl":"10.1016/j.vlsi.2026.102661","url":null,"abstract":"<div><div>This paper introduces a high-precision, FPGA-based analog signal generator that fundamentally departs from conventional, template-based approaches by mathematically synthesizing each analog pulse in real time. Unlike systems relying on pre-recorded or pre-defined waveform memories, the proposed architecture dynamically computes every sample of double-exponential pulses on-the-fly within reconfigurable FPGA logic. Leveraging the AMD Xilinx ZYNQ 7010 SoC, the system ensures that every pulse is uniquely tailored on demand, with full control over rise time, decay time, amplitude, and pile-up effects. This real-time, parameter-driven signal generation enables the accurate emulation of complex detector signals, including overlapping events and user-defined spectral distributions, while guaranteeing deterministic timing and minimal processor overhead.</div><div>Experimental results demonstrate that the platform can precisely reproduce the analog characteristics and statistical features of diverse scintillation detector responses, outperforming commercial solutions limited to simple exponential or static waveform outputs. The modular, runtime-reconfigurable design supports dual-channel, high-fidelity operation and can be extended to broader application domains, including medical signal emulation and telecommunication waveform synthesis. By eliminating dependence on static pulse templates, this work establishes a new standard for flexibility, realism, and accuracy in embedded hardware testing and detector development.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102661"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145980163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

RO-like ring-based TRNG with adaptive mode switching for enhanced entropy Harvesting 基于自适应模式切换的类ro环TRNG增强熵收集

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2026-05-01 Epub Date: 2026-01-03 DOI: 10.1016/j.vlsi.2025.102640

Jinlin Chen , Huaguo Liang , Yingchun Lu , Liang Yao

引用次数: 0