Integration-The Vlsi Journal最新文献_第3页

An efficient XOR-free implementation of polar encoder for reconfigurable hardware 可重构硬件极性编码器的高效无 XOR 实现

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-24 DOI: 10.1016/j.vlsi.2024.102291

Navin Kumar , Deepak Kedia , Gaurav Purohit

{"title":"An efficient XOR-free implementation of polar encoder for reconfigurable hardware","authors":"Navin Kumar , Deepak Kedia , Gaurav Purohit","doi":"10.1016/j.vlsi.2024.102291","DOIUrl":"10.1016/j.vlsi.2024.102291","url":null,"abstract":"<div><div>— This paper presents a novel approach to implementing an XOR-Free architecture of the non-systematic polar encoder (NSPE) for 5G radio. The optimization of XOR logic for hardware (HW) implementation is essential to reduce delay and power consumption. The proposed architecture for NSPE replaces XOR operations with combinational logical patterns, and some redundant patterns are removed with the help of bit manipulation to make it more efficient. The design infers multiplexers (2:1 or 4:1) and inverters as its functional units, making the design adequate and effective in alleviating HW complexity. The XOR-Free encoder performs the same functionality as the XOR-based conventional encoder. We have written a MATLAB script that generates Verilog hardware description language (HDL) code for fully or partially parallel polar encoders tailored to specific code lengths (<em>N</em>) and degrees of parallelism (<em>M</em>). A comparative analysis of various fully and partially parallel encoders with the XOR-Free algorithm is presented. The implementation results show that the proposed architectures are more efficient in terms of HW cost, power consumption, throughput, and latency.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102291"},"PeriodicalIF":2.2,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142359424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism 利用 Zk-SNARK 的多级并行性，加速 Zk-SNARK 中的大规模多标量乘法运算

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-24 DOI: 10.1016/j.vlsi.2024.102286

Ning Wang , Feng Wang , Pengcheng Hua , Xu Zhao , Zhilei Chai

{"title":"Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism","authors":"Ning Wang , Feng Wang , Pengcheng Hua , Xu Zhao , Zhilei Chai","doi":"10.1016/j.vlsi.2024.102286","DOIUrl":"10.1016/j.vlsi.2024.102286","url":null,"abstract":"<div><div>In the context of zk-SNARK, MSM emerges as a major computational bottleneck, particularly due to its high computational and memory overhead. In this work, we exploit multiple levels of parallelism to effectively accelerate largescale MSM in zk-SNARKs. Firstly, a distributed parameter generation method is proposed in this paper to replace that of centralized method. Based on this methodology, the paper realizes a system with extraordinary scalability, capable of computing large-scale MSMs. Subsequently, the approach presented in this paper elevates the computation of Bellperson, the most prominent zero-knowledge proof system in real-world applications, from a single-node computation to a clustering mode, significantly enhancing its computational performance – a crucial advancement for practical applications. Finally, we implement a multi-level, fully parallelised MSM computing system by leveraging hierarchical sub-task partitioning and cross-node communication optimization, thereby thoroughly exploiting parallelism at diverse granularities. Experimental results show that in the cluster scenario, the proposed approach achieves acceleration ratios of approximately 3.60 and 6.50 times compared to the cutting-edge heterogeneous version Bellperson in dual-node and quad-node settings, respectively. On a single node, the proposed optimization approach achieves an acceleration ratio of 1.38 times compared to the current State-of-the-Art MSM calculation module of cuZK, outperforms the industry-popular Bellman by 186 times and the Bellperson by 1.96 times.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102286"},"PeriodicalIF":2.2,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142419987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Lorenz’s state equations as RC filters 作为 RC 滤波器的洛伦兹状态方程

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-23 DOI: 10.1016/j.vlsi.2024.102284

Isaac Campos-Cantón

引用次数: 0

PDQRRFF: Poisson-distributed quantum random reversible flip flop generator for BIST PDQRRFF：用于 BIST 的泊松分布式量子随机可逆触发器发生器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-23 DOI: 10.1016/j.vlsi.2024.102289

Kannan R , Vidhya K

{"title":"PDQRRFF: Poisson-distributed quantum random reversible flip flop generator for BIST","authors":"Kannan R , Vidhya K","doi":"10.1016/j.vlsi.2024.102289","DOIUrl":"10.1016/j.vlsi.2024.102289","url":null,"abstract":"<div><div>Reversible logic has gained popularity recently because it allows circuits to use significantly less power. Due to the inherent reversibility of quantum operation, there is enormous interest in designing and optimizing reversible circuits. In this work, a new gate named as transvidkan gate, Quantum Random Reversible Flip Flop, Sequence generator, and Build in Self-Test (BIST) has been proposed. Quantum Random Reversible Flip Flop (QRRFF) is an emerging technology that is used in a variety of apps that use modern security and encryption systems. For creating a random string, typical approaches combine an entropy source with an elimination or bit-generation system. Quantum computing reversible logic chips and Low-power design are emerging as intriguing research topics. A classical logic-based 8-bit reversible comparator is represented using existing reversible gates. This study provides a BIST-based architecture for a comparator design that reduces the garbage outputs, quantum cost, and constant inputs. According to simulation result, the proposed approach outperforms traditional methods in terms of hardware complexity and quantum cost.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102289"},"PeriodicalIF":2.2,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142327647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Innovative feedback approach for high-performance low-voltage current mirror 用于高性能低压电流镜的创新反馈方法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-18 DOI: 10.1016/j.vlsi.2024.102283

Astha Dadheech, Nikhil Raj, Divyang Rawal

{"title":"Innovative feedback approach for high-performance low-voltage current mirror","authors":"Astha Dadheech, Nikhil Raj, Divyang Rawal","doi":"10.1016/j.vlsi.2024.102283","DOIUrl":"10.1016/j.vlsi.2024.102283","url":null,"abstract":"<div><p>The paper presents an approach to increase the performance in terms of input and output resistance of a low voltage flipped voltage follower (FVF) based current mirror. The proposed technique consists of substituting the main output transistor with a network of transistors in a feedback arrangement, designed to improve the output resistance. Furthermore, a low saturation onset transistor approach is used to improve the performance. Such an approach also helped in reducing the input resistance of the current mirror, which ranges in ohms. A wide current range of up to 1 mA is achieved at a minimal current transfer error of 0.38 %. This feedback mechanism-based current mirror exhibits an output resistance of 29.61 GΩ, an input resistance of 30.45 Ω, and a bandwidth of 1.464 GHz. The proposed current mirror runs on ±0.5 V supply voltage. The robustness of the proposed circuit is evaluated through process corner analysis, temperature mismatch assessment, and Monte-Carlo simulations. The performance characteristics of the proposed current mirror have been validated and simulated using Cadence Virtuoso and Spectre simulations on 0.18 μm UMC technology. The validation process included both pre-layout and post-layout simulation results.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102283"},"PeriodicalIF":2.2,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142272574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A local positive feedback loop-reused technique for enhancing performance of folded cascode amplifier 提高折叠式级联放大器性能的局部正反馈回路重复使用技术

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-12 DOI: 10.1016/j.vlsi.2024.102277

Xiaosong Wang, Xiao Zhao, Yu Zhang, Chen Wang, Liyuan Dong

引用次数: 0

Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability 在 RISC-V 处理器微体系结构中集成纠错和检测技术以提高可靠性

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-12 DOI: 10.1016/j.vlsi.2024.102282

Aswin Sreekumar, Bolupadra Sai Shankar, B. Naresh Kumar Reddy

{"title":"Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability","authors":"Aswin Sreekumar, Bolupadra Sai Shankar, B. Naresh Kumar Reddy","doi":"10.1016/j.vlsi.2024.102282","DOIUrl":"10.1016/j.vlsi.2024.102282","url":null,"abstract":"<div><p>An essential consideration in processor design is ensuring reliability, particularly in demanding environments such as outer space and nuclear plants. To mitigate the effects of errors and enable error recovery, processors need to incorporate fault tolerance techniques. One common type of error is SEU (Single Event Upset), which affects various microelectronic devices including microprocessors, microcontrollers, and semiconductor memory devices. While error mitigation techniques have been developed for processors based on architectures like ARM (Advanced RISC Machine) and MIPS (Million Instructions Per Second), there is a gap in research for open-source ISAs (Instruction Set Architecture) like RISC-V, which this paper aims to address. This paper focuses on designing a fault-tolerant microarchitecture for a RISC-V processor that can correct one-bit errors, detect up to two-bit errors, and integrate lockstep and pipeline rollback features at a lower LUTs (Look Up Tables) consumption by re-using the same hardware pipeline for error mitigation and recovery through instruction mimicking. By incorporating these features, the proposed approach enhances the system’s fault tolerance by detecting and correcting errors caused by transient events and achieves a lower effective die size upon realization compared to contemporary works. The proposed microarchitecture design was simulated and synthesized using the Vivado Design Suite 2023.1 and implemented on a Zynq 7000 SoC ZC702 Evaluation Kit.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102282"},"PeriodicalIF":2.2,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142242434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A general and accurate pattern search method for various scenarios 适用于各种情况的通用精确模式搜索法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-11 DOI: 10.1016/j.vlsi.2024.102281

Congyi Zhang , Xu He , Hao Sang , Hengzhou Yuan , Dawei Liu , Yang Guo

引用次数: 0

Synchronous control of memristive hindmarsh-rose neuron models with extreme multistability 具有极端多稳定性的记忆性后马什-蔷薇神经元模型的同步控制

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-10 DOI: 10.1016/j.vlsi.2024.102280

Shaohui Yan, Jialong Wang, Jincai Song

引用次数: 0

Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB 两阶段有序逃逸路由与 LP 和启发式算法相结合，用于大型印刷电路板

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-07 DOI: 10.1016/j.vlsi.2024.102270

Disi Lin , Chuandong Chen , Rongshan Wei , Qinghai Liu , Huan He , Ziran Zhu , Zhifeng Lin , Jianli Chen

{"title":"Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB","authors":"Disi Lin , Chuandong Chen , Rongshan Wei , Qinghai Liu , Huan He , Ziran Zhu , Zhifeng Lin , Jianli Chen","doi":"10.1016/j.vlsi.2024.102270","DOIUrl":"10.1016/j.vlsi.2024.102270","url":null,"abstract":"<div><div>The Ordered Escape Routing (OER) problem, which is an NP-hard problem, is critical to PCB design. Primary methods based on integer linear programming (ILP) work well on small-scale PCBs with fewer pins. However, when dealing with large-scale instances, traditional ILP strategies frequently cause time violations as the number of variables increases due to time-consuming preprocessing. In addition, heuristic algorithms have a time advantage when dealing with specific problems. In this paper, We propose an efficient two-stage escape routing method that employs LP for global routing and uses a heuristic algorithm to deal with the path intersection problem to minimize wiring length and runtime for large-scale PCBs. We first model the OER problem as a min-cost multi-commodity flow problem and use ILP to solve it. Then, we relax the non-crossing constraints and transform the ILP model into an LP model to reduce the runtime. we also construct a crossing graph according to the intersection of routing paths and propose a heuristic algorithm to locate congestion quickly. Finally, we reduce the local area capacity and allow global automatic congestion optimization. Compared with the state-of-the-art work, experimental results show that our method can reduce the routing time by 60% and handle larger-scale PCB escape routing problems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102270"},"PeriodicalIF":2.2,"publicationDate":"2024-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142323992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0