Integration-The Vlsi Journal最新文献_第3页

Few-shot learning GNN-EQL model with gm/ID method for analog integrated circuit design 基于gm/ID方法的模拟集成电路设计的少次学习GNN-EQL模型

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-16 DOI: 10.1016/j.vlsi.2025.102551

Xin Xiong, Hongjian Zhou, Pingqiang Zhou

{"title":"Few-shot learning GNN-EQL model with gm/ID method for analog integrated circuit design","authors":"Xin Xiong, Hongjian Zhou, Pingqiang Zhou","doi":"10.1016/j.vlsi.2025.102551","DOIUrl":"10.1016/j.vlsi.2025.102551","url":null,"abstract":"<div><div>Analog integrated circuit design typically involves extensive analytical derivations to evaluate circuit performance metrics. Although SPICE simulations facilitate efficient prediction of these metrics, the simulation process remains time-consuming as the dimensionality of circuit parameters increases. In this article, we propose integrating Graph Neural Networks (GNN) with Equation Learner Networks (EQL), employing them as pretrained models within a limited range of design parameters. Our results demonstrate that datasets constructed using the <span><math><mrow><msub><mrow><mi>g</mi></mrow><mrow><mi>m</mi></mrow></msub><mo>/</mo><msub><mrow><mi>I</mi></mrow><mrow><mi>D</mi></mrow></msub></mrow></math></span> method capture design points more efficiently compared to the random sampling of width-to-length (<span><math><mrow><mi>W</mi><mo>/</mo><mi>L</mi></mrow></math></span>) ratios. Furthermore, experimental validation indicates that the pretrained GNN-EQL model achieves superior performance compared to other pretrained models when the parameter range expands across three different amplifier designs. Finally, our approach significantly reduces the required samples by up to 20X when adapting the pretrained model to broader parameter ranges, compared to training a new model from scratch.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102551"},"PeriodicalIF":2.5,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145097536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-performance OTFS transmitter on FPGA: A hybrid HLS/VHDL design 基于FPGA的高性能OTFS发射机：HLS/VHDL混合设计

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-16 DOI: 10.1016/j.vlsi.2025.102542

Djaballah Merouane , Ayat Louiza , Ouchikh Rabah , Azzaz Mohammed Salah

{"title":"High-performance OTFS transmitter on FPGA: A hybrid HLS/VHDL design","authors":"Djaballah Merouane , Ayat Louiza , Ouchikh Rabah , Azzaz Mohammed Salah","doi":"10.1016/j.vlsi.2025.102542","DOIUrl":"10.1016/j.vlsi.2025.102542","url":null,"abstract":"<div><div>Rapid advances in high-speed vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) communications require innovative waveforms to address the challenges posed by mobility and the doubly dispersive nature of communication channels. Orthogonal Time Frequency Space (OTFS), a waveform operating in the delay-Doppler domain, offers enhanced robustness and performance under these conditions. This paper presents the implementation of an OTFS transmitter on a Field-Programmable Gate Array (FPGA), focusing on the ZedBoard platform. Two variants of the OTFS transmitter were developed and evaluated for data sizes of 16, 32, and 64 symbols. To benchmark their performance against conventional architectures, the implementations were re-evaluated on the 7vx485tfg1157-1 FPGA. The first variant achieved a throughput efficiency of 82.46 Tbps/W, utilizing 1,844 LUTs at an operating frequency of 147.8 MHz. The second variant demonstrated a higher throughput efficiency of 199.6 Tbps/W, consuming 3,094 LUTs with a maximum operating frequency of 149.52 MHz. These results highlight a significant improvement in performance while ensuring an optimal balance between resource utilization, latency, and throughput efficiency. This work underscores the potential of OTFS for real-time applications in future wireless networks, particularly in 6G communication scenarios.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102542"},"PeriodicalIF":2.5,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145109849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware implementation of a novel chaos-based cryptosystem for secure image transmission 一种新的基于混沌的安全图像传输密码系统的硬件实现

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-16 DOI: 10.1016/j.vlsi.2025.102554

Rim Amdouni , Mahdi Madani , Mohamed Ali Hajjaji , El Bay Bourennane , Mohamed Atri

{"title":"Hardware implementation of a novel chaos-based cryptosystem for secure image transmission","authors":"Rim Amdouni , Mahdi Madani , Mohamed Ali Hajjaji , El Bay Bourennane , Mohamed Atri","doi":"10.1016/j.vlsi.2025.102554","DOIUrl":"10.1016/j.vlsi.2025.102554","url":null,"abstract":"<div><div>In today's interconnected world, securing digital image transmissions is crucial to protect sensitive information against modern cyber threats. This paper presents a hardware implementation of a novel chaos-based symmetric cryptosystem for secure grayscale image transmission. The proposed method integrates a 4D Rössler hyperchaotic system as a key generator with a lightweight 128-bit block cipher comprising whitening, pixel-bit permutation, block-pixel permutation, and chaos-based S-box substitution. Both the key generator and the encryption engine are implemented on a Xilinx Virtex UltraScale VCU108 FPGA using VHDL.</div><div>The proposed chaotic PRNG successfully passes the NIST SP 800-22 statistical tests, demonstrating strong randomness properties. Experimental results show that the cryptosystem achieves high security and robust resistance to statistical and differential attacks, with entropy values up to 7.9997, NPCR average of 99.62 %, and UACI equal to 33.4 %. The hardware implementation achieves a throughput of 3.49 Gbps with low power consumption of 0.098 W, confirming its suitability for real-time embedded image encryption applications. These results validate the effectiveness of the proposed design in meeting high-speed, low-power, and high-security requirements for modern image transmission systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102554"},"PeriodicalIF":2.5,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145109852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of electronic system for linearization of sinusoidal characteristics of cascaded tunneling magneto-resistance sensor 级联隧道磁阻传感器正弦特性线性化电子系统设计

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-13 DOI: 10.1016/j.vlsi.2025.102540

Ritu Ranjan, Sanjoy Mandal

引用次数: 0

A quality-configurable approximate cache design based on NAND-like SOT MRAM with high energy efficiency 一种基于类nand的高能效SOT MRAM的高质量可配置近似缓存设计

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-13 DOI: 10.1016/j.vlsi.2025.102541

Zhengyi Hou , Luyao Shi , Yan Qiao , Bi Wang , Bi Wu , Lirida Naviner , Zhaohao wang

{"title":"A quality-configurable approximate cache design based on NAND-like SOT MRAM with high energy efficiency","authors":"Zhengyi Hou , Luyao Shi , Yan Qiao , Bi Wang , Bi Wu , Lirida Naviner , Zhaohao wang","doi":"10.1016/j.vlsi.2025.102541","DOIUrl":"10.1016/j.vlsi.2025.102541","url":null,"abstract":"<div><div>Approximate computing is widely used for decreasing the power and area consumption of a system since there are many error-tolerant multimedia applications nowadays. NAND-like spin–orbit torque magnetic tunnel junction (SOT-MTJ) as a novel non-volatile multi-bit memory device with high speed and high area efficiency, has a location-related stochastic switching mechanism, which can achieve 100% accuracy for high significant bits (HSBs) while storing low significant bits (LSBs) approximately through the decrease of writing pulse width. Thus, it is highly suitable for the approximate storage and updating of data. In this work, we proposed a quality-configurable last-level cache based on the NAND-like SOT MRAM by utilizing location-related stochastic switching, where the write pulse width is used as an accuracy knob to switch between precise storage and approximate storage. A highly efficient write operation and a specific pipeline read policy are designed to adapt the novel cell structure and application scenarios. To evaluate the performance of the proposal, a circuit-level simulation model NVSim and a set of approximate computing benchmarks Axbench are utilized. By reducing the writing pulse width of the NAND-like SOT MTJs from 3 ns to 1 ns, the improvement of energy and latency are achieved by 42% and 64% with only 3.4% accuracy loss on average for image processing benchmarks.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102541"},"PeriodicalIF":2.5,"publicationDate":"2025-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145097539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient, reliable, and secure PUF architecture with temperature invariance and ML attack resilience 高效、可靠、安全的PUF架构，具有温度不变性和ML攻击弹性

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-12 DOI: 10.1016/j.vlsi.2025.102538

Nitish Kumar , Aakif Nehal , Aditya Vikram Singh , Kavindra Kandpal , Manish Goswami

{"title":"Efficient, reliable, and secure PUF architecture with temperature invariance and ML attack resilience","authors":"Nitish Kumar , Aakif Nehal , Aditya Vikram Singh , Kavindra Kandpal , Manish Goswami","doi":"10.1016/j.vlsi.2025.102538","DOIUrl":"10.1016/j.vlsi.2025.102538","url":null,"abstract":"<div><div>Physically Unclonable Functions (PUFs) provide an advanced hardware solution for secure authentication and key generation. They utilize the inherent, unpredictable, and unavoidable differences created during semiconductor manufacturing. These unique characteristics, specific to each chip, are harnessed in PUF circuits to produce distinct and unclonable identifiers for devices. By taking advantage of these random variations present in modern semiconductor processes, PUFs strengthen both hardware and software security, offering a dependable and effective way to protect digital systems from potential threats. In this proposed paper, the use of efficient circuit design for Current starved, aging resilient inverter, and linear feedback shift register (LFSR) have resulted in the increase of reliability from 80.06% to 98.06%. The uniqueness, uniformity, and bit-aliasing achieved are of 49.21%, 50.08% and 50.08% , respectively, for a wide temperature range spanning from -40°C to 120°C and reduction of power dissipation to approximately 1.57 times less than the conventional Arbiter PUF. The pre-layout and post-layout Simulation results showed a delay of 1.08 ns and 1.95 ns respectively. The NIST test also revealed that the proposed design had randomness in the response. The proposed designs are also experimentally verified using Xilinx Vivado and implemented on Digilent Basys 3 Artix-7 FPGA, with minimum hardware resources, with a bit generation rate of 95 Mb/sec. Additionally, the proposed design exhibits resilience against machine learning (ML) attacks, with a prediction accuracy of approximately 55% to 79.3% for the PUF responses.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102538"},"PeriodicalIF":2.5,"publicationDate":"2025-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhanced functional verification models that ensure the full functionality of an A-PLL device 增强的功能验证模型，确保A-PLL器件的全部功能

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-12 DOI: 10.1016/j.vlsi.2025.102520

Mariam Maurice , Rich Edelman , Mohamed Dessouky , Ashraf Salem

引用次数: 0

High accurate approximate adders using hybrid gates 采用混合门的高精度近似加法器

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-12 DOI: 10.1016/j.vlsi.2025.102552

Yongqiang Zhang, Jiao Qin, Xin Cheng, Guangjun Xie

引用次数: 0

Implementation of imprecise multipliers using 2-bit adder for image processing 用2位加法器实现图像处理中的不精确乘法器

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-10 DOI: 10.1016/j.vlsi.2025.102510

Parthibaraj Anguraj , Thiruvenkadam Krishnan

{"title":"Implementation of imprecise multipliers using 2-bit adder for image processing","authors":"Parthibaraj Anguraj , Thiruvenkadam Krishnan","doi":"10.1016/j.vlsi.2025.102510","DOIUrl":"10.1016/j.vlsi.2025.102510","url":null,"abstract":"<div><div>The inexact multiplier architecture represents a foundational element of approximate computing, serving a critical function across diverse error-tolerant applications. This paper delves into the complexities of three distinct inexact multiplier designs, each meticulously optimized for image processing applications. This work introduces a strategic partitioning of the partial product stage into smaller segments, subsequently implementing decoder algorithms, truncation methods, exact 2-bit adder and proposed multiplexer-based imprecise 2-bit adder circuits. These resulting 8<span><math><mo>×</mo></math></span> 8 imprecise multipliers exhibit advantageous error metrics and streamlined design complexity. When benchmarked against traditional inexact multipliers, these architectures achieve notable reductions in both area and power consumption, as validated by modeling conducted via the Cadence RTL compiler with TSMC’s 90 nm technology. The proposed approximation model demonstrates substantial area and power reductions of 37.19% and 46.14%, respectively, compared to precise multipliers, all while sustaining acceptable error metrics. Additionally, the developed 8<span><math><mo>×</mo></math></span> 8 multipliers surpass other approximate multiplier architectures in performance metrics, making them particularly effective for image multiplication and sharpening.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102510"},"PeriodicalIF":2.5,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimization of fourth order noise transfer function using PSO algorithm for delta sigma modulator δ σ调制器四阶噪声传递函数的粒子群算法优化

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-08 DOI: 10.1016/j.vlsi.2025.102539

Arockia Twinkle J , Srinivasan R , Premanand V. Chandramani

引用次数: 0