Multi-cell lightweight high-throughput TRNG based on selector clock driving and XOR feedback

True Random Number Generators (TRNGs) play a pivotal role in encryption, digital signatures, and related fields. As the most critical component of a TRNG, the entropy source determines the quality of randomness. Current TRNGs primarily rely on specific physical randomness sources as entropy sources, but this approach struggles to balance low resource overhead and high throughput. This paper proposes a multi-cell TRNG architecture based on selector clock driving and XOR feedback to achieve high throughput and superior randomness quality. The design employs D flip-flops and combinational logic gates, utilizing multiple ring oscillators (ROs) connected to selector inputs to generate clock signals and data inputs for the D flip-flops. A feedback structure with XOR gates enhances randomness. The proposed TRNG was implemented on Xilinx Virtex-6, Spartan-6, and Artix-7 FPGA boards. Experimental results demonstrate that the TRNG achieves a throughput of 433 Mb/s using only 41 LUTs and 10 D flip-flops, while passing NIST, AIS-31, autocorrelation, TESTU01, and restart tests without post-processing.