Memory device based on memristor-diode crossbar and control CMOS logic for spiking neural network hardware

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
A.N. Busygin , A.D. Pisarev , S. Yu Udovichenko , A.H.A. Ebrahim
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引用次数: 0

Abstract

A compact electrical circuit of a memory device based on a memristor-diode crossbar array and peripheral CMOS control logic has been developed. The peripheral logic circuit is digitally controlled and allows reading and changing the state of individual memristors. This functionality is necessary to store and transfer the synaptic states of the neural network to another neural network to avoid re-learning. Simple original electrical circuits of input and output drivers utilizing standard rectangular impulses to control memristor-diode crossbar were created. These circuits ensure the operation of the memristor matrix both as part of the hardware spiking neural network and in the modes of writing and reading the state of the memristors. Exclusion of multiple DACs and ADCs in the electrical circuits of input and output crossbar conductor drivers made it possible to significantly reduce the occupied area on the chip. On the basis of numerical modeling using the experimental characteristics of memristors the maximum size of crossbar in the developed circuit and the influence of parasitic currents on the processes of writing and reading the state of memristors are estimated. Connection of the peripheral logic circuit in the memristor leads to a limitation of the maximum size of the crossbar due to additional parasitic currents. A method of compensating the influence of parasitic currents on the process of setting memristors in a given state by varying the duration of programming pulses is proposed.
基于忆阻二极管交叉棒和控制CMOS逻辑的存储器件用于尖峰神经网络硬件
提出了一种基于忆阻二极管横条阵列和外设CMOS控制逻辑的紧凑存储电路。外围逻辑电路是数字控制的,允许读取和改变单个忆阻器的状态。这种功能对于存储和传递神经网络的突触状态到另一个神经网络以避免重新学习是必要的。利用标准矩形脉冲控制忆阻二极管横栅的输入和输出驱动器的简单原始电路被创建。这些电路保证了忆阻器矩阵作为硬件尖峰神经网络的一部分以及在读写忆阻器状态的模式下的运行。在输入和输出横排导体驱动器的电路中排除多个dac和adc,可以显著减少芯片上的占用面积。在利用忆阻器的实验特性进行数值模拟的基础上,估计了所开发电路中横条的最大尺寸以及寄生电流对忆阻器状态写入和读取过程的影响。由于附加的寄生电流,在忆阻器中连接外设逻辑电路会限制横条的最大尺寸。提出了一种通过改变编程脉冲的持续时间来补偿寄生电流对给定状态下设置忆阻器过程的影响的方法。
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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