用于抵抗机器学习攻击的轻量级通用PUF框架

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Tianming Ni , Fei Li , Zhengfeng Huang , Aibin Yan , Senling Wang , Xiaoqing Wen , Mu Nie , Jingchang Bian
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引用次数: 0

摘要

物理不可克隆函数(PUF)是一种有吸引力的低成本安全原语,不需要存储,并且可以抵抗逆向工程。然而,经典puf非常容易受到机器学习攻击,并且大多数抵抗这些攻击的尝试都会消耗过多的资源。为了解决这个问题,本文提出了一个轻量级的通用PUF框架。首先,该框架采用分割处理引入结构非线性,达到自我保护的目的。其次,对前段响应、前段挑战和后段挑战进行异或处理,引入挑战混淆,大大增强了PUF的抗机器学习能力。此外,对于可配置的RO PUF,本文提出了一种新的基于mux的RO(称为MRO),可节省50%的资源。基于PUF框架实现的两段MRO-MRO实例的可靠性、一致性和唯一性都接近理想值。综合实验表明,该PUF具有框架可扩展、资源开销低、抗机器学习攻击能力强等优点。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A lightweight general PUF framework for resisting machine learning attacks
Physical Unclonable Function (PUF) is an attractive and low-cost security primitive that requires no storage and is resistant to reverse engineering. However, classical PUFs are highly vulnerable to machine learning attacks, and most attempts to resist these attacks consume excessive resources. To address this challenge, a lightweight general PUF framework is proposed in this paper. Firstly, the framework adopts segmentation processing to introduce structural nonlinearities for the purpose of self-protection. Secondly, the pre-segment response, pre-segment challenges and post-segment challenges undergo XOR processing to introduce challenges obfuscation, which greatly enhances the machine learning resistance of the PUF. In addition, for configurable RO PUF, a novel MUX-based RO (called MRO) is proposed in this paper, which can save resources by 50 %. Implementing a two-segment MRO-MRO instance based on the proposed PUF framework results in reliability, uniformity, and uniqueness that are close to the ideal values. Comprehensive experiments demonstrate that the proposed PUF has the advantages of scalable framework, low resource overhead, and strong resistance to machine learning attacks.
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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