Efficient CNFET-based ternary logic design with emphasis on half-adder and multiplier circuits

This paper presents a novel methodology for synthesizing efficient ternary logic devices, specifically focusing on a Ternary Half-Adder (THA) and Ternary Multiplier (TMUL). A new ternary circuit design is proposed to minimize the Power-Delay Product (PDP) and reduce transistor count compared to existing approaches. Essential ternary gates, such as inverters, AND/NAND, and OR/NOR gates, along with the THA and TMUL, are implemented using Carbon Nanotube Field-Effect Transistors (CNFETs), chosen for their potential of high integration density and low intrinsic delay. Comprehensive simulations using HSPICE demonstrate significant performance improvements, including an average of 43% reduction in transistor count and an average of 83% decrease in PDP for the THA design compared to some prior topologies. The TMUL design also exhibits substantial PDP enhancements and transistor count reduction, achieving an average of 37% in transistor count and 65% in PDP enhancements, comparing with various benchmarks. These findings highlight that, despite a slight increase in power consumption, the proposed designs are well-suited for high-performance, low-delay, and compact (low-area) applications in advanced digital systems, confirming CNFETs as a promising alternative to CMOS in Multi-Valued Logic circuit design.