GATOR: A Graph Neural Network based Design Anomaly Predictor

Several design issues detected in the physical design stages of the Application Specific Integrated Circuits (ASIC) flow are attributed to poorly written Register Transfer Level (RTL) codes. Such issues are complex to resolve using iterative synthesis, placement optimization and engineering change orders (ECOs). As a result, design closure is delayed, impacting the overall timeline of the chip tape-out. Detection of such RTL constructs early in the design flow can help tackle the downstream issues in the physical design stages like congestion hotspots, high cell/pin density in the core area, timing degradation and timing design rule violations. This work presents a graph learning based approach to detect such design anomalies in the RTL. GATOR, a synthesis tool-independent, parameterized, and customizable framework to detect design anomalies, is presented. It allows flexibility in model generation based on the degree of strictness set by the ASIC designers. This GNN-based approach is highly accurate in detecting RTL design anomalies, with an average accuracy of 98.62% for the most strict threshold combination and an average inference time of 2.75 s, resulting in a speedup of 8.59$\times$ compared to algorithm-based checks presented in this work to determine the design anomalies, which can reduce multiple iterations in the physical design stages.