Zhisheng Chen , Hongjin Su , Bohan Dong , Genggeng Liu , Xing Huang
{"title":"SDCLR:可扩展的双控制层路由连续流微流控生物芯片与最小化的控制端口","authors":"Zhisheng Chen , Hongjin Su , Bohan Dong , Genggeng Liu , Xing Huang","doi":"10.1016/j.vlsi.2025.102445","DOIUrl":null,"url":null,"abstract":"<div><div>Recent advancements in continuous-flow microfluidic biochips have led to highly integrated lab-on-a-chip systems with complex functionality and minimized control ports. Despite these advancements, achieving efficient control-layer routing under strict valve synchronization remains a significant challenge. Clustering more valves into the same group can reduce the usage of control ports but necessitates building a larger routing tree to meet the length-matching requirements of synchronized valve groups, significantly reducing the routing resources available for other valves and diminishing routing feasibility. To strike an optimized balance between control port usage and routing feasibility, this paper proposes a scalable dual-control layer routing method called SDCLR, aimed at optimizing routing feasibility while minimizing the number of control ports. The main features of SDCLR include a DBSCAN-based valve readdressing to optimize routing area allocation, a conflict-aware layer assignment to minimize resource contention, and a synchronized-driven routing framework to ensure precise synchronized valve operations. Experimental results show that SDCLR performs excellently in terms of routability, control port number, and timing requirements.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102445"},"PeriodicalIF":2.5000,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"SDCLR: Scalable Dual Control-Layer Routing for continuous-flow microfluidic biochips with minimized control ports\",\"authors\":\"Zhisheng Chen , Hongjin Su , Bohan Dong , Genggeng Liu , Xing Huang\",\"doi\":\"10.1016/j.vlsi.2025.102445\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>Recent advancements in continuous-flow microfluidic biochips have led to highly integrated lab-on-a-chip systems with complex functionality and minimized control ports. Despite these advancements, achieving efficient control-layer routing under strict valve synchronization remains a significant challenge. Clustering more valves into the same group can reduce the usage of control ports but necessitates building a larger routing tree to meet the length-matching requirements of synchronized valve groups, significantly reducing the routing resources available for other valves and diminishing routing feasibility. To strike an optimized balance between control port usage and routing feasibility, this paper proposes a scalable dual-control layer routing method called SDCLR, aimed at optimizing routing feasibility while minimizing the number of control ports. The main features of SDCLR include a DBSCAN-based valve readdressing to optimize routing area allocation, a conflict-aware layer assignment to minimize resource contention, and a synchronized-driven routing framework to ensure precise synchronized valve operations. Experimental results show that SDCLR performs excellently in terms of routability, control port number, and timing requirements.</div></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":\"104 \",\"pages\":\"Article 102445\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2025-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926025001026\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025001026","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
SDCLR: Scalable Dual Control-Layer Routing for continuous-flow microfluidic biochips with minimized control ports
Recent advancements in continuous-flow microfluidic biochips have led to highly integrated lab-on-a-chip systems with complex functionality and minimized control ports. Despite these advancements, achieving efficient control-layer routing under strict valve synchronization remains a significant challenge. Clustering more valves into the same group can reduce the usage of control ports but necessitates building a larger routing tree to meet the length-matching requirements of synchronized valve groups, significantly reducing the routing resources available for other valves and diminishing routing feasibility. To strike an optimized balance between control port usage and routing feasibility, this paper proposes a scalable dual-control layer routing method called SDCLR, aimed at optimizing routing feasibility while minimizing the number of control ports. The main features of SDCLR include a DBSCAN-based valve readdressing to optimize routing area allocation, a conflict-aware layer assignment to minimize resource contention, and a synchronized-driven routing framework to ensure precise synchronized valve operations. Experimental results show that SDCLR performs excellently in terms of routability, control port number, and timing requirements.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.