SDCLR:可扩展的双控制层路由连续流微流控生物芯片与最小化的控制端口

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Zhisheng Chen , Hongjin Su , Bohan Dong , Genggeng Liu , Xing Huang
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引用次数: 0

摘要

连续流微流体生物芯片的最新进展导致了具有复杂功能和最小化控制端口的高度集成的片上实验室系统。尽管取得了这些进步,但在严格的阀门同步下实现有效的控制层路由仍然是一个重大挑战。将更多的阀门聚在同一组中可以减少控制端口的使用,但需要建立更大的路由树来满足同步阀门组的长度匹配要求,这大大减少了其他阀门的可用路由资源,降低了路由的可行性。为了在控制端口利用率和路由可行性之间取得最佳平衡,本文提出了一种可扩展的双控制层路由方法SDCLR,旨在优化路由可行性的同时最小化控制端口的数量。SDCLR的主要特点包括基于dbscan的阀门重设,以优化路由区域分配,冲突感知层分配,以最大限度地减少资源争用,以及同步驱动的路由框架,以确保精确同步的阀门操作。实验结果表明,SDCLR在路由可达性、控制端口号和定时要求方面都有很好的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
SDCLR: Scalable Dual Control-Layer Routing for continuous-flow microfluidic biochips with minimized control ports
Recent advancements in continuous-flow microfluidic biochips have led to highly integrated lab-on-a-chip systems with complex functionality and minimized control ports. Despite these advancements, achieving efficient control-layer routing under strict valve synchronization remains a significant challenge. Clustering more valves into the same group can reduce the usage of control ports but necessitates building a larger routing tree to meet the length-matching requirements of synchronized valve groups, significantly reducing the routing resources available for other valves and diminishing routing feasibility. To strike an optimized balance between control port usage and routing feasibility, this paper proposes a scalable dual-control layer routing method called SDCLR, aimed at optimizing routing feasibility while minimizing the number of control ports. The main features of SDCLR include a DBSCAN-based valve readdressing to optimize routing area allocation, a conflict-aware layer assignment to minimize resource contention, and a synchronized-driven routing framework to ensure precise synchronized valve operations. Experimental results show that SDCLR performs excellently in terms of routability, control port number, and timing requirements.
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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