Power Gated-SRAM and novel header–footer multiplexer based ultra low power Look-Up Table design

In this paper we propose a two-level power gating technique which could incorporate significant leakage power reduction in pass transistor (PTL) and transmission gate (T-Gate) based look up table (LUT), designed using 45 nm generic library from cadence. First level power gating at SRAM array resulted in reduced subthreshold and gate leakage across the devices. A novel Header/Footer logic has been implemented to power-gate MUX logic of LUT. Unlike conventional header/footer schemes that only cut off the supply or ground to reduce leakage, our diode-connected header and feedback-controlled footer enable parallel output level restoration while simultaneously suppressing leakage. The feedback-controlled footer (NFD) ensures that weak logic levels from the multiplexer do not propagate to the output buffer, thereby reducing subthreshold and gate leakage. The Power-gated SRAM average power dissipation has been observed to reduce from 6.09 pW to 1.884 pW (write-1 operation). Power gating in the SRAM array resulted in a three order magnitude reduction in average power from 17.01$\mu$ W to 153.05 nW at pass transistor-based LUT level. Similar average power reduction up to 3-orders have also been observed for T-Gate based MUX-LUT with power gated SRAMs from 16.42$\mu$ W to 688.3 nW. The values were further reduced by more than three orders for both PTL and T-Gate based designs when novel header/footer logic was applied at the MUX level. Post-layout simulations further validate that parasitic effects reduce overall power dissipation compared to the pre-layout results for conventional and gated SRAM based LUTs. Additionally, the CLB implementation demonstrates ultra-low power of 389.8 pW in low-performance mode (HP=0), highlighting the practical advantage of the proposed architecture over conventional LUT-based designs. The implementation of proposed design impose no observable delay of data transfer between input of SRAM to final output of CLB.