Low-power hardware architecture of optimized logarithmic square rooter with enhanced error compensation for error-tolerant systems

Approximate computing optimizes arithmetic circuits by reducing power and resource usage for applications that tolerate some error, offering hardware advantages over traditional designs. A key component, the square rooter, is resource-intensive, especially in image and signal processing, making its optimization crucial. This work presents a low-power, resource-efficient optimized logarithmic square rooter (OLSR) that calculates the square root of a $2n$-bit unsigned integer using addition and shift operations with minimal error. The proposed approximate square rooter outperforms the precise restoring array-based design by using 73% fewer resources, achieving a 53% faster operation, and delivering 81% better power savings. Despite some trade-offs in approximation error, the results are highly acceptable, with a normalized mean error distance (NMED) of $1.08\times 10^{-2}$, a mean relative error distance (MRED) of $1.77\times 10^{-2}$, a mean error distance (MED) of 2.77, and a maximum error distance (ED${}_{\text{max}}$) of 11. This design balances efficiency and precision well. The design is implemented on an Artix-7 FPGA using Verilog-HDL and validated in Xilinx Vivado. Comparisons with four other approaches highlight the OLSR’s strong balance between accuracy and hardware efficiency, with outstanding performance in the Sobel edge detection and Image enhancement application.