Design of dynamic prairie dog optimization based variable length conditional counter enabled multiplier with improved slack time and power

Abstract

Multipliers are major components in any data rendering, logical computations and the unit of Digital Signal Processing (DSP). The particular events counting carried out by using the electronic devices called Binary Counters (BC) that displays as well as stores the count numbers. While providing an effective counting operation, the Binary Counter (BC) incorporates a sequential logic circuit with a clock signal. This work presented a novel Variable Length Conditional Counter (VLCC) design using the Dynamic Prairie Dog Optimization (DPDO) algorithm for delay mitigation. Using the proposed DPDO algorithm, this study performs path delay reduction, enhances the slack interval, and designs the multiplier at various frequencies. The circuit based slack interval evaluates the frequency operation maximization. To compare state-of-the-art works, the slack time performance analyzed and implementation handles based on Mentor Graphics EDA simulator. CMOS technology effectuates 8-bit binary multiplier implementation. The slack time enhancement as well as computational delay mitigation performances of proposed DPDO algorithm performance surpassed other state-of-the-art works.