基于0.18 μm CMOS技术的S到Ku波段宽带低压低功耗上转换混频器

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2025-09-07 DOI:10.1016/j.vlsi.2025.102536

Jun-Da Chen, Liang-Chung Shen

{"title":"基于0.18 μm CMOS技术的S到Ku波段宽带低压低功耗上转换混频器","authors":"Jun-Da Chen, Liang-Chung Shen","doi":"10.1016/j.vlsi.2025.102536","DOIUrl":null,"url":null,"abstract":"<div><div>This paper presents a wideband up-conversion mixer chip in TSMC 0.18-μm CMOS technology that covers the frequency range of 2–18 GHz. The architecture is based on a folded Gilbert cell mixer. The transconductance stage uses an inverting amplifier architecture with G<sub>m</sub>-boosted technology to increase the conversion gain, utilizing an inductive source degenerate design to achieve the best linearity. The load inductor uses a transformer coupling method to minimize chip area while enhancing inductance. The measured results for the proposed mixer show 10–16.2 dB conversion gain, −1.8 to −6 dBm input third-order intercept point (IIP3), the overall DC power consumption is 3.69 mW, while the supply voltage is 1 V. The conversion gain is 14.7 dB over the 3–16 GHz range, with a flat increase of ±1.5 dB. The measured LO-to-RF port-to-port isolation is 22.3–33 dB. The total chip size of the up-conversion is 1.2 mm<sup>2</sup>.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102536"},"PeriodicalIF":2.5000,"publicationDate":"2025-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An S to Ku band wideband low-voltage low-power up-conversion mixer in 0.18-μm CMOS technology\",\"authors\":\"Jun-Da Chen, Liang-Chung Shen\",\"doi\":\"10.1016/j.vlsi.2025.102536\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>This paper presents a wideband up-conversion mixer chip in TSMC 0.18-μm CMOS technology that covers the frequency range of 2–18 GHz. The architecture is based on a folded Gilbert cell mixer. The transconductance stage uses an inverting amplifier architecture with G<sub>m</sub>-boosted technology to increase the conversion gain, utilizing an inductive source degenerate design to achieve the best linearity. The load inductor uses a transformer coupling method to minimize chip area while enhancing inductance. The measured results for the proposed mixer show 10–16.2 dB conversion gain, −1.8 to −6 dBm input third-order intercept point (IIP3), the overall DC power consumption is 3.69 mW, while the supply voltage is 1 V. The conversion gain is 14.7 dB over the 3–16 GHz range, with a flat increase of ±1.5 dB. The measured LO-to-RF port-to-port isolation is 22.3–33 dB. The total chip size of the up-conversion is 1.2 mm<sup>2</sup>.</div></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":\"106 \",\"pages\":\"Article 102536\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2025-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926025001932\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025001932","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

摘要

本文提出了一种采用台积电0.18 μm CMOS技术的宽带上变频混频器芯片，其工作频率范围为2-18 GHz。该建筑基于折叠的吉尔伯特单元混频器。跨导级采用反相放大器架构和gm增强技术来增加转换增益，利用电感源简并设计来实现最佳线性度。负载电感采用变压器耦合的方式，在增强电感的同时减小芯片面积。测量结果表明，该混频器的转换增益为10-16.2 dB，输入三阶截距点（IIP3）为−1.8 ~−6 dBm，总直流功耗为3.69 mW，电源电压为1 V。在3-16 GHz范围内，转换增益为14.7 dB，平均增加±1.5 dB。测量的低电平到射频端口到端口的隔离度为22.3 - 33db。上转换的总芯片尺寸为1.2 mm2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

An S to Ku band wideband low-voltage low-power up-conversion mixer in 0.18-μm CMOS technology

This paper presents a wideband up-conversion mixer chip in TSMC 0.18-μm CMOS technology that covers the frequency range of 2–18 GHz. The architecture is based on a folded Gilbert cell mixer. The transconductance stage uses an inverting amplifier architecture with G_m-boosted technology to increase the conversion gain, utilizing an inductive source degenerate design to achieve the best linearity. The load inductor uses a transformer coupling method to minimize chip area while enhancing inductance. The measured results for the proposed mixer show 10–16.2 dB conversion gain, −1.8 to −6 dBm input third-order intercept point (IIP3), the overall DC power consumption is 3.69 mW, while the supply voltage is 1 V. The conversion gain is 14.7 dB over the 3–16 GHz range, with a flat increase of ±1.5 dB. The measured LO-to-RF port-to-port isolation is 22.3–33 dB. The total chip size of the up-conversion is 1.2 mm².

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.