A survey on vertical interconnection and topology of three-dimensional network-on-chip

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2025-08-29 DOI:10.1016/j.vlsi.2025.102529

Yuan Zhang , Zewei Jing , Qinghai Yang , Nan Cheng , Huaxi Gu , Kyung Sup Kwak

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引用次数: 0

Abstract

The three-dimensional network-on-chip (3D NoC) has been proposed with the continuous advancement of integrated circuits (ICs) to address the inherent limitations of conventional two-dimensional NoC (2D NoC) architectures. 3D NoCs introduce direct vertical inter-layer electrical connections, enabling the integration of additional processing elements (PEs) within a limited area, hence significantly enhancing integration density and communication efficiency. However, the performance and scalability of 3D NoCs are highly dependent on vertical interconnection technologies and topology designs. In this survey, we discuss the development of 2D and 3D IC/NoC, providing a comprehensive overview of various vertical interconnection technologies evolved from conventional bonding to through-via (especially through-silicon-via) and to contactless connection. Additionally, we categorize the topologies of 3D NoCs based on their shapes and compare their degree, diameter, connections, and bisection bandwidth. The current challenges and future research opportunities are discussed to provide a foundation for the continued advancement and development in 3D NoCs.

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三维片上网络垂直互连与拓扑研究进展

三维片上网络（3D NoC）是随着集成电路（ic）的不断发展而提出的，以解决传统二维NoC （2D NoC）架构的固有局限性。3D noc引入了直接的垂直层间电气连接，可以在有限的区域内集成额外的处理元件（pe），从而显着提高集成密度和通信效率。然而，3D noc的性能和可扩展性高度依赖于垂直互连技术和拓扑设计。在本调查中，我们讨论了2D和3D IC/NoC的发展，全面概述了从传统键合到通孔（特别是通硅孔）和非接触式连接的各种垂直互连技术。此外，我们根据它们的形状对3D noc的拓扑结构进行了分类，并比较了它们的度、直径、连接和二分带宽。讨论了当前的挑战和未来的研究机会，为3D noc的持续进步和发展奠定了基础。

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.