具有硬件共享的ATSS-PUF,用于安全的原位存储电路

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Shutong Zhang , Pengjun Wang , Mengfan Xv , Bo Chen , Yuejun Zhang
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引用次数: 0

摘要

工业物联网(IoT)边缘节点迫切需要兼顾低功耗、恶劣工况下密钥稳定性和硬件效率的加密方案,但现有技术存在密钥误码率高、硬件资源开销大、数据安全性不足等缺陷。为了解决这些问题,本文提出了一种四模可重构原位存储单元,该单元实现了密钥生成、动态筛选、外差加密和密集状态存储功能的硬件复用,并结合了主动时间倾斜筛选机制和在对称路径中注入可控延迟扰动来筛选不稳定密钥位。实测结果表明,在−20℃~ 80℃的温度波动和0.7 ~ 1.2 v的电压扰动下,电路PUF响应分别降至1.9%和2.9%的误码率,PUF响应的随机性达到99.8%,片间汉明距离达到49.57%,自相关仅为0.0224,通过了NIST的随机性测试,并具有抗侧信道攻击和抗粗攻击的能力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
ATSS-PUF with hardware sharing for secure in-situ memory circuit
Industrial Internet of Things (IoT) edge nodes urgently need encryption schemes that take into account key stability and hardware efficiency under low-power consumption and harsh working conditions, but existing technologies are limited by defects such as high key BER, high hardware resource overhead, and insufficient data security. To solve these problems, this paper proposes a four-mode reconfigurable in-situ memory unit, which accomplishes the hardware multiplexing of key generation, dynamic screening, heterodyne encryption and dense state storage functions, and combines the active time-tilted screening mechanism with the injection of controlled delayed perturbations into the symmetric path to screen the unstable key bits. The measured results demonstrate that the circuit PUF response drops to 1.9 % and 2.9 % BER under temperature fluctuation of −20 °C–80 °C and voltage perturbation of 0.7–1.2V, respectively, and the randomness of the PUF response reaches 99.8 %, the inter-slice Hamming distance reaches 49.57 %, the autocorrelation is only 0.0224, which passes the randomness test of NIST, and the capability of anti-side-channel attack and anti-brutal attack is provided.
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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