Thermal and Congestion-aware Deadlock-free Application-specific Novel Halted Routing Strategy in 3D NoCs

3D-Mesh NoCs containing hundreds of cores suffer from excessive traffic loads in the routers which often lead to the creation of thermal hotspots as well as severe routing congestion issues. The state-of-the-art deterministic routing techniques fail to balance this huge traffic loads due to their rigid path selection policy. On the other hand, adaptive routing techniques require additional temperature- and traffic-detection and management circuits as well as computation-intensive router architectures. Therefore, to harness the fundamental benefits of Network-on-Chip (NoC) architectures such as simplicity and scalability, this work implements a novel deterministic routing technique which efficiently adjusts the routing paths for a target application by adding a halt router in the path between the source and destination routers. A combination of Discrete Particle Swarm Optimization (DPSO) and Simulated Annealing (SA) algorithms have been used to optimally select the halt routers’ positions such that both the traffic load variance of the network and the peak temperature of the chip get reduced. Based on the offline positioning of halt routers a halted routing algorithm has been used to transfer the packets from source to halt router and then halt to destination router. PARSEC and SPLASH-2 benchmarks are used to generate the target traffic patterns. The experimental results show that the proposed halted routing strategy is able to produce significant reduction in both chip temperature (up to 10 °C) and traffic-load variance (up to 42%) when applied on the standard deterministic routing techniques - Thermal-aware Selective Detour ($TSD$), Downward-XYZ ($DR$), $XYZ$, and $ZXY$ routings.