FPGA routing congestion prediction combining DAGNN and GCN

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Tingyuan Nie, Yang Du, Da Guo, Kun Zhao
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引用次数: 0

Abstract

The issue of routing congestion is intractable due to the high complexity of FPGA (Field-Programmable Gate Array) design. Accurately predicting routing congestion in the early stages of the design process can shorten the overall design cycle. In the placement stage, this paper proposes an FPGA routing congestion prediction framework combining a deep adaptive graph neural network (DAGNN) and a graph convolutional network (GCN), the so-called DAGNN-GCN. DAGNN captures deep neighborhood topological information, focusing primarily on complex network features. Based on the hierarchical inclusion relationship between G-cells and cells, the extracted topological information is mapped geometrically onto the original geometric features and inflated to generate input feature vectors. These vectors are then fed into the GCN to train the routing congestion prediction of the model. Experimental results on the ISPD 2016 dataset demonstrate that the proposed method achieves Kendall, Spearman, and Pearson correlation coefficients of 0.57, 0.72, and 0.76, respectively, representing improvements of 16.33%, 5.88%, and 13.43% over the state-of-the-art LHNN method. Ablation studies further validate the efficiency of the proposed features in routing congestion prediction.
结合DAGNN和GCN的FPGA路由拥塞预测
由于FPGA(现场可编程门阵列)设计的高度复杂性,路由拥塞问题非常棘手。在设计过程的早期阶段准确预测路由拥塞可以缩短整个设计周期。在放置阶段,本文提出了一种结合深度自适应图神经网络(DAGNN)和图卷积网络(GCN)的FPGA路由拥塞预测框架,即DAGNN-GCN。DAGNN捕获深度邻域拓扑信息,主要关注复杂网络特征。基于g -cell与cell之间的层次包含关系,将提取的拓扑信息几何映射到原始几何特征上,并进行膨胀生成输入特征向量。然后将这些向量输入GCN以训练模型的路由拥塞预测。在ISPD 2016数据集上的实验结果表明,该方法的Kendall、Spearman和Pearson相关系数分别为0.57、0.72和0.76,比目前最先进的LHNN方法分别提高了16.33%、5.88%和13.43%。消融研究进一步验证了所提特征在路由拥塞预测中的有效性。
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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