{"title":"结合DAGNN和GCN的FPGA路由拥塞预测","authors":"Tingyuan Nie, Yang Du, Da Guo, Kun Zhao","doi":"10.1016/j.vlsi.2025.102530","DOIUrl":null,"url":null,"abstract":"<div><div>The issue of routing congestion is intractable due to the high complexity of FPGA (Field-Programmable Gate Array) design. Accurately predicting routing congestion in the early stages of the design process can shorten the overall design cycle. In the placement stage, this paper proposes an FPGA routing congestion prediction framework combining a deep adaptive graph neural network (DAGNN) and a graph convolutional network (GCN), the so-called DAGNN-GCN. DAGNN captures deep neighborhood topological information, focusing primarily on complex network features. Based on the hierarchical inclusion relationship between G-cells and cells, the extracted topological information is mapped geometrically onto the original geometric features and inflated to generate input feature vectors. These vectors are then fed into the GCN to train the routing congestion prediction of the model. Experimental results on the ISPD 2016 dataset demonstrate that the proposed method achieves Kendall, Spearman, and Pearson correlation coefficients of 0.57, 0.72, and 0.76, respectively, representing improvements of 16.33%, 5.88%, and 13.43% over the state-of-the-art LHNN method. Ablation studies further validate the efficiency of the proposed features in routing congestion prediction.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102530"},"PeriodicalIF":2.5000,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"FPGA routing congestion prediction combining DAGNN and GCN\",\"authors\":\"Tingyuan Nie, Yang Du, Da Guo, Kun Zhao\",\"doi\":\"10.1016/j.vlsi.2025.102530\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>The issue of routing congestion is intractable due to the high complexity of FPGA (Field-Programmable Gate Array) design. Accurately predicting routing congestion in the early stages of the design process can shorten the overall design cycle. In the placement stage, this paper proposes an FPGA routing congestion prediction framework combining a deep adaptive graph neural network (DAGNN) and a graph convolutional network (GCN), the so-called DAGNN-GCN. DAGNN captures deep neighborhood topological information, focusing primarily on complex network features. Based on the hierarchical inclusion relationship between G-cells and cells, the extracted topological information is mapped geometrically onto the original geometric features and inflated to generate input feature vectors. These vectors are then fed into the GCN to train the routing congestion prediction of the model. Experimental results on the ISPD 2016 dataset demonstrate that the proposed method achieves Kendall, Spearman, and Pearson correlation coefficients of 0.57, 0.72, and 0.76, respectively, representing improvements of 16.33%, 5.88%, and 13.43% over the state-of-the-art LHNN method. Ablation studies further validate the efficiency of the proposed features in routing congestion prediction.</div></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":\"105 \",\"pages\":\"Article 102530\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2025-09-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926025001877\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025001877","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
FPGA routing congestion prediction combining DAGNN and GCN
The issue of routing congestion is intractable due to the high complexity of FPGA (Field-Programmable Gate Array) design. Accurately predicting routing congestion in the early stages of the design process can shorten the overall design cycle. In the placement stage, this paper proposes an FPGA routing congestion prediction framework combining a deep adaptive graph neural network (DAGNN) and a graph convolutional network (GCN), the so-called DAGNN-GCN. DAGNN captures deep neighborhood topological information, focusing primarily on complex network features. Based on the hierarchical inclusion relationship between G-cells and cells, the extracted topological information is mapped geometrically onto the original geometric features and inflated to generate input feature vectors. These vectors are then fed into the GCN to train the routing congestion prediction of the model. Experimental results on the ISPD 2016 dataset demonstrate that the proposed method achieves Kendall, Spearman, and Pearson correlation coefficients of 0.57, 0.72, and 0.76, respectively, representing improvements of 16.33%, 5.88%, and 13.43% over the state-of-the-art LHNN method. Ablation studies further validate the efficiency of the proposed features in routing congestion prediction.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.