Lanxiang Wang, B. Liu, X. Gong, P. Guo, Qian Zhou, L. Chua, W. Zou, C. Hatem, T. Henry, Y. Yeo
{"title":"Self-crystallization and reduced contact resistivity by hot phosphorus ion implant in germanium-tin alloy","authors":"Lanxiang Wang, B. Liu, X. Gong, P. Guo, Qian Zhou, L. Chua, W. Zou, C. Hatem, T. Henry, Y. Yeo","doi":"10.1109/VLSI-TSA.2014.6839659","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839659","url":null,"abstract":"We investigated the effect of phosphorus ion (P+) implant temperature on the material properties of epitaxial GeSn alloy and the electrical characteristics of GeSn n+/p diodes. Hot P+ implant maintains the single crystallinity of GeSn during implant. In addition, samples implanted at elevated temperature followed by a subsequent RTA at 450 °C for 3 minutes achieve a lower contact resistivity compared with those implanted at room temperature, indicating a higher P dopant activation.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124441756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electron ballistic current enhancement of Ge1−xSnx FinFETs","authors":"H. Lan, C. W. Liu","doi":"10.1109/VLSI-TSA.2014.6839656","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839656","url":null,"abstract":"The indirect-direct transition of Ge1-xSnx at Sn content 6.5% is simulated by nonlocal empirical pseudopotential method. The non-parabolicity band of Γ valley is considered for confined mass, density of state, and conductivity mass for the electron ballistic current calculation of Ge1-xSnx FinFETs. The integration of alloying Sn content and applying external stress enhances the ballistic current due to carriers transferring from indirect L valleys with small injection velocity to direct Γ valley and other indirect L valleys with high injection velocity.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122971405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. R. Verma, Z. Shaoqiang, C. K. Wai, Tan Juan Boon, R. Nair
{"title":"Foundry RF technologies","authors":"P. R. Verma, Z. Shaoqiang, C. K. Wai, Tan Juan Boon, R. Nair","doi":"10.1109/VLSI-TSA.2014.6839703","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839703","url":null,"abstract":"Landscape of semiconductor technologies and manufacturing has been changing in general and RF technologies in specific from IDMs to foundries and from exotic III-V compounds to the silicon. Tremendous advantage of RF performance from nanometer technologies, exponential increase in scalability, availability of high resistivity and engineered SOI substrates have opened doors for the convergence of all sorts of RF applications to silicon based RF technologies. Wafer foundries having been in the leading position of silicon based technologies are going to be benefited with this convergence and all design houses will have access to the same with minimal investments. This paper talks about the three major forces which are helping to converge all consumer RF application integrated circuits to total silicon based solutions with minimum form factor.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115255297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Chien, Ding-Yeong Wang, Sheng-Huang Huang, K. Shen, Shan-Yi Yang, J. Shyu, Keng-Ming Kuo, Young-Shying Chen, Yung-Hung Wang, T. Ku, D. Deng
{"title":"Scaling properties of perpendicular MTJ with dual-CoFeB/MgO interfaces and step-etch structure","authors":"C. Chien, Ding-Yeong Wang, Sheng-Huang Huang, K. Shen, Shan-Yi Yang, J. Shyu, Keng-Ming Kuo, Young-Shying Chen, Yung-Hung Wang, T. Ku, D. Deng","doi":"10.1109/VLSI-TSA.2014.6839662","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839662","url":null,"abstract":"We had built and studied the size scaling effect of perpendicular magnetic tunnel junctions (p-MTJs) with dual MgO/CoFeB interface and step-etch structure. Although the spin-torque-transfer (STT) switching current reduces with MTJ area, the current density increases. Our micromagnetic simulations verify that this is an intrinsic property of STT switching. The switching mode shifts gradually from coherent switching in small junctions to incoherent in large junctions. The energy density of coherent switching is higher and demands higher spin current density. At same current density, smaller size takes longer time to switch. Fortunately, the write efficiency (Δ/Isw) is higher for smaller MTJ.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115365295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact of channel doping on the device and NBTI performance in FinFETs for low power applications","authors":"A. Sachid, C. Hu","doi":"10.1109/VLSI-TSA.2014.6839654","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839654","url":null,"abstract":"We present device-level characterization of digital, analog and NBTI parameters for p-FinFETs with different channel doping. We show that using channel doping we can trade-off device and NBTI performance. In p-FinFETs, Arsenic doped channel has better digital and analog performance and Boron doped channel has superior NBTI performance. Forward body bias reduces NBTI degradation in p-FinFETs.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"16 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132348878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Roadway to innovation","authors":"Ronald M. Martino","doi":"10.1109/VLSI-TSA.2014.6839630","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839630","url":null,"abstract":"Electronic innovation is becoming increasingly more important in the evolution of our society. Noble goals of extending healthy lives with improving medical capabilities, creating a cleaner environment, eliminating auto fatalities, and creating a connected infrastructure around the “Internet of Things” all center on electronic innovation. These goals are being driven by both legislation and consumer demand, which is leading to accelerated system challenges driving a strong need for integration of disparate functional blocks and exponential scaling of content. A central focus in this evolution is the automobile. Emission standards are driving systems from single core, simple computational units to highly integrated, scaled out, safe and secure domain controllers, which host multiple diverse software environments. Shifts toward autonomous driving are leading to integrated sensing systems leveraging advanced algorithms for detection classification and safe decision making. The strong demand for connected vehicles is resulting in revolutionary changes to the vehicle network and communication infrastructure embedded in the automobile. We will explore how these automotive trends translate to future challenges for technology platforms, integrated circuit module development, system-on-chip integration, design of safe systems, and implementation of secure but diagnosable systems.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121675556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Tsui, Ko-Chin Chang, B. Shew, Heng-Yuan Lee, M. Tsai
{"title":"Investigation of radiation hardness of HfO2 resistive random access memory","authors":"B. Tsui, Ko-Chin Chang, B. Shew, Heng-Yuan Lee, M. Tsai","doi":"10.1109/VLSI-TSA.2014.6839675","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839675","url":null,"abstract":"Radiation hardness of HfO2-based resistive random-access memory (RRAM) is investigated using extreme ultra-violet (EUV) and X-ray as radiation source. The low-resistance state (LRS) is immune to irradiation, but temporary change of the high-resistance state (HRS) and endurance degradation could be observed at high total irradiation dose (TID). A physical model is proposed to explain these observations. It is concluded that the HfO2-based RRAM can be operated in high radiation environment, and EUV can be use to fabricate high-density RRAM array.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126728179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sheng-Yen Chien, P. Lin, Hung-Yu Chen, C. Lin, Y. King
{"title":"Self-convergent trimming of embedded logic compatible OTP memory for VT variation reduction in low voltage SRAMs","authors":"Sheng-Yen Chien, P. Lin, Hung-Yu Chen, C. Lin, Y. King","doi":"10.1109/VLSI-TSA.2014.6839666","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839666","url":null,"abstract":"Self-align nitride (SAN) logic NVM cell coupled by metal gate WL is incorporated into a low-voltage SRAM design. Replacing pull-down transistors in SRAM cells, SAN OTP devices is used to compensate mismatches between the two branches. Through a self-convergent blanket programming operation, the new SRAM cell has been demonstrated to effectively suppress process variation effect, especially critical in low-voltage applications.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124011643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. F. Chang, L. Ji, Y. Chen, F. Zhou, T. Tsai, K. Chang, M. Chen, T. Chang, B. Fowler, E. Yu, J. Lee
{"title":"High-density nano-pillar SiOx-based resistive switching memory using nano-sphere lithography to fabricate a one diode - one resistor (1D-1R) architecture","authors":"Y. F. Chang, L. Ji, Y. Chen, F. Zhou, T. Tsai, K. Chang, M. Chen, T. Chang, B. Fowler, E. Yu, J. Lee","doi":"10.1109/VLSI-TSA.2014.6839674","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839674","url":null,"abstract":"A highly compact, one diode - one resistor (1D-1R) nano-pillar device architecture has been demonstrated using nano-sphere lithography (NSL) to fabricate SiOx-based resistive switching (RS) memory. The intrinsic SiOx-based resistive switching element and Si-based PN diode are self-aligned on the epitaxial silicon wafer using NSL and a deep-Si-etch process without using conventional photolithography. The DC electrical performance, an AC pulse response in the 50 ns regime, capability for multi-bit operation, and high readout margin immunity for sneak path issue demonstrate good potential for high-speed nonvolatile memory (NVM). The NSL fabrication process is an efficient, economical approach to enable large-scale patterning of 1D-1R architectures while providing excellent NVM performance for future applications.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123085604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"More than Moore foundry: Challenges for process technology, process characterization and design enablement to address complex cyber physical systems in harsh environments","authors":"Steven Chen","doi":"10.1109/VLSI-TSA.2014.6839699","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839699","url":null,"abstract":"Summary form only given. This presentation focuses on More than Moore technologies - the integration of additional features in digital CMOS technologies. Such additional features include high-voltage transistors with operating voltages up to 200V; non-volatile memories for trimming, program and data storage; and sensors for pressure or magnetic flux measurements. Complexity even increases when the circuit is operated in harsh environments with temperatures up to 175 degrees C. The covered application space spans motion and gesture sensing in today's mobile devices; automotive applications such as alternators, controllers for brushless DC electric motor with LIN or CAN interfaces as well as medical applications such as ultrasonic transducer arrays. Ideally, design engineers are able to achieve all of their design targets with a minimal number of iterations or even at first silicon to reduce time to market. The talk will help engineers understand the complexity of their designs and provide guidance on how to achieve their design targets. This presentation describes how to identify the right process technology, process characterization requirements in the context of high-temperature operations, and multiple design challenges such as ESD robustness, die size constraints, low noise and low power, and high reliability.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129711821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}