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Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)最新文献

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SOI technology: An opportunity for RF designers? SOI技术:射频设计人员的机遇?
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839644
J. Raskin
{"title":"SOI technology: An opportunity for RF designers?","authors":"J. Raskin","doi":"10.1109/VLSI-TSA.2014.6839644","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839644","url":null,"abstract":"This last decade Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency commercial applications, reaching cutoff frequencies close to 500 GHz. SOI also presents the major advantage of providing high resistivity substrate capabilities, leading to substantially reduced substrate RF losses. High Resistivity SOI is commonly foreseen as a promising substrate for radio frequency integrated circuits and mixed signal applications. In this paper, based on several experimental and simulation results, the interest, limitations but also possible future improvements of the SOI MOS technology are presented.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116700831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Compact modeling of Random Telegraph Noise in nanoscale MOSFETs and impacts on digital circuits 纳米级mosfet随机电报噪声的紧凑建模及其对数字电路的影响
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839681
Mulong Luo, Runsheng Wang, Jing Wang, Shaofeng Guo, Jibin Zou, Ru Huang
{"title":"Compact modeling of Random Telegraph Noise in nanoscale MOSFETs and impacts on digital circuits","authors":"Mulong Luo, Runsheng Wang, Jing Wang, Shaofeng Guo, Jibin Zou, Ru Huang","doi":"10.1109/VLSI-TSA.2014.6839681","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839681","url":null,"abstract":"The complexity of Random Telegraph Noise (RTN) under digital circuit operations makes it difficult to predict its impacts without accurate modeling and simulation. However, properly integrating RTN into circuit simulation is challenging due to its stochastic nature. In this paper, RTN is comprehensively modeled and embedded into BSIM. A circuit simulation methodology based on industry-standard EDA tools is proposed, resolving the stochastic property, the AC effects, and the coupling of RTN and circuits that are crucial for accurate predictions of impacts of RTN. Using the compact model and proposed method, impacts of RTN on RO and SRAM are demonstrated, which ascertains their applicability to different type of circuits.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121124119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A high density Twin-Gate OTP cell in pure 28nm CMOS process 采用纯28nm CMOS工艺制备的高密度双栅OTP电池
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839664
W. Hsiao, C. Y. Mei, W. Shen, Tzong-Sheng Chang, Y. Chih, Y. King, C. Lin
{"title":"A high density Twin-Gate OTP cell in pure 28nm CMOS process","authors":"W. Hsiao, C. Y. Mei, W. Shen, Tzong-Sheng Chang, Y. Chih, Y. King, C. Lin","doi":"10.1109/VLSI-TSA.2014.6839664","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839664","url":null,"abstract":"A high density high-k gate dielectric breakdown OTP cell with a self-aligned twin-gate isolation in pure 28nm HKMG process is demonstrated. With a merged spacer isolation formed by two tiny metal gates, the OTP cells can be well isolated with an ultra small cell size of 0.0441μm2 in pure 28nm CMOS logic process. The Twin-Gate OTP memory adopts low voltage high-k dielectric breakdown mechanism to obtain 104 times of On/Off ratio by a low program voltage of 4V in 20μs. A tiny and excellent Twin-Gate isolation with wide program and temperature margins has been successfully achieved in this OTP cell. Superior disturbs immunity and data retention further support the new logic OTP cell to be a promising solution in advanced logic NVM applications.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121422505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Investigating MLC variation of filamentary and non-filamentary RRAM 研究丝状和非丝状RRAM的MLC变化
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839684
Jen-Chieh Liu, I-Ting Wang, Chung-Wei Hsu, Wun-Cheng Luo, T. Hou
{"title":"Investigating MLC variation of filamentary and non-filamentary RRAM","authors":"Jen-Chieh Liu, I-Ting Wang, Chung-Wei Hsu, Wun-Cheng Luo, T. Hou","doi":"10.1109/VLSI-TSA.2014.6839684","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839684","url":null,"abstract":"Distinct statistical differences between the HBM non-filamentary RRAM and popular filamentary RRAM are highlighted in this study. The HBM RRAM features little cycle-to-cycle variation on both resistance and SET/RESET time, which enlarges the design window of MLC operation. A reliable four-level MLC operation have been demonstrated in the HBM device, suggesting its great potential for high-density data storage applications.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"87 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127417068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Selenium segregation optimization for 10 nm node contact resistivity 10 nm节点接触电阻率的硒偏析优化
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839658
C. Ni, K. V. Rao, F. Khaja, S. Sharma, B. Zheng, J. Ramalingam, J. Gelatos, J. Lei, C. Chang, A. Mayur, N. Variam, R. Hung, A. Brand
{"title":"Selenium segregation optimization for 10 nm node contact resistivity","authors":"C. Ni, K. V. Rao, F. Khaja, S. Sharma, B. Zheng, J. Ramalingam, J. Gelatos, J. Lei, C. Chang, A. Mayur, N. Variam, R. Hung, A. Brand","doi":"10.1109/VLSI-TSA.2014.6839658","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839658","url":null,"abstract":"Contact resistivity (ρ<sub>C</sub>) reduction for n-SD (source/drain) with Se<sup>+</sup> implant was evaluated for different integration schemes. It is found that Se<sup>+</sup> implant energy is one of the most critical process parameters for ρ<sub>C</sub> improvement, achieved by placing the Se<sup>+</sup> peak close to silicide (TiSi<sub>2</sub> or NiPtSi)/Si interface and minimized implant damage. Recovery of implant damage to silicide and n-SD region was achieved with millisecond laser anneal, while minimizing dopant deactivation. This work demonstrated a viable integration pathway to realize low ρ<sub>C</sub> solution for n-SD for 10 nm node.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129366449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analytical solutions for breakdown voltage and electrical characteristics of STI DEMOS transistors STI演示晶体管击穿电压和电气特性的解析解
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839682
H. Tsai, Y. Yadav, R. Liou, K. Wu, Y. Lin, C. Lien
{"title":"Analytical solutions for breakdown voltage and electrical characteristics of STI DEMOS transistors","authors":"H. Tsai, Y. Yadav, R. Liou, K. Wu, Y. Lin, C. Lien","doi":"10.1109/VLSI-TSA.2014.6839682","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839682","url":null,"abstract":"A CMOS compatible high-voltage STI DEMOS transistor is fabricated and its electrical characteristics studied. A method is used to find the breakdown voltage of this two-dimensional STI DEMOS structure theoretically. A breakdown voltage model, which relates the breakdown voltage to the effective N well doping concentration NB and the width of the accumulation region χa, is derived. The predictions of this model agree very well with both the experimental data and with the TCAD simulations.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129156208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel Si-based X'tal oscillator device using 3D integration technologies 采用三维集成技术的新型硅基X轴振荡器装置
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839693
J. Shih, Yen-Chi Chen, C. Chiu, C. Lo, Kuan-Neng Chen
{"title":"A novel Si-based X'tal oscillator device using 3D integration technologies","authors":"J. Shih, Yen-Chi Chen, C. Chiu, C. Lo, Kuan-Neng Chen","doi":"10.1109/VLSI-TSA.2014.6839693","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839693","url":null,"abstract":"A novel Si-based X'tal oscillator device (1.2 mm × 1.0 mm) is demonstrated by using 3D integration technologies. It is distinct from conventional X'tal oscillator device with ceramics and metal lid. The novel Si-based X'tal oscillator device shows no leakage path, and passes the hermetic encapsulation test and reliability investigation. In addition, the novel device shows the excellent electrical characteristics and provides the possibility to replace the conventional fabrication approach for the next generation products.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130703511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Accurate RRAM transient currents during forming 成形过程中精确的RRAM瞬态电流
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839688
P. Shrestha, D. Nminibapiel, J. Campbell, J-H Kim, C. Vaz, K. Cheung, H. Baumgart
{"title":"Accurate RRAM transient currents during forming","authors":"P. Shrestha, D. Nminibapiel, J. Campbell, J-H Kim, C. Vaz, K. Cheung, H. Baumgart","doi":"10.1109/VLSI-TSA.2014.6839688","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839688","url":null,"abstract":"The magnitude of overshoot current during forming has been shown to be a serious issue. Recently we showed that the overshoot duration is equally important in impacting device performance. Shorter duration overshoot in the range of ns yields better performance, suggesting extremely short forming pulse to be desirable. But investigation of such short forming transients is severely limited experimentally due to parasitic. In this study we demonstrate a technique to accurately de-embed these parasitic components yielding accurate forming current transients in the ps range, paving the road to careful study of the forming process.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126284536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Improved multi-level control of RRAM using pulse-train programming 利用脉冲序列编程改进了RRAM的多级控制
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839673
Liang Zhao, Hong-Yu Chen, Shih-Chieh Wu, Zizhen Jiang, Yuan Shimeng, T. Hou, H. Wong, Y. Nishi
{"title":"Improved multi-level control of RRAM using pulse-train programming","authors":"Liang Zhao, Hong-Yu Chen, Shih-Chieh Wu, Zizhen Jiang, Yuan Shimeng, T. Hou, H. Wong, Y. Nishi","doi":"10.1109/VLSI-TSA.2014.6839673","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839673","url":null,"abstract":"Multi-level cell (MLC) capability in RRAM is attractive for reducing the cost per bit. Based on the filamentary switching mechanisms, we propose a pulse-train programming scheme to achieve reliable and uniform MLC controls without the need of any read-verification operation. By applying the novel scheme to a 3 bit/cell RRAM device, the uniformity of resistance distribution can be improved up to 80%.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127761369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Impact of pulse rise time on programming of cross-point RRAM arrays 脉冲上升时间对交叉点RRAM阵列编程的影响
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839689
Rui Liu, Hong-Yu Chen, Haitong Li, Peng Huang, Liang Zhao, Zhe Chen, Feifei Zhang, Bing Chen, Lifeng Liu, Xiaoyan Liu, B. Gao, Shimeng Yu, Y. Nishi, H. Wong, Jinfeng Kang
{"title":"Impact of pulse rise time on programming of cross-point RRAM arrays","authors":"Rui Liu, Hong-Yu Chen, Haitong Li, Peng Huang, Liang Zhao, Zhe Chen, Feifei Zhang, Bing Chen, Lifeng Liu, Xiaoyan Liu, B. Gao, Shimeng Yu, Y. Nishi, H. Wong, Jinfeng Kang","doi":"10.1109/VLSI-TSA.2014.6839689","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839689","url":null,"abstract":"The role of pulse rise time during RRAM programming of cross-point arrays is investigated. The parasitic components in memory arrays is shown to result in distortion and degradation of the applied pulse on the memory cells (compared to the ideal/as-generated pulse), and will potentially cause programming failure. For the first time, the impact of pulse rising edge on the switching voltage is measured. The degradation and distortion of the applied pulse will result in programming failure when the pulse width becomes narrow. Thus, extra attention must be paid for large scale cross-point architecture in high-speed applications.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133543893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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