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Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)最新文献

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A survey of technical trend of ADAS and autonomous driving ADAS与自动驾驶技术发展趋势综述
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834940
Ryosuke Okuda, Yuki Kajiwara, K. Terashima
{"title":"A survey of technical trend of ADAS and autonomous driving","authors":"Ryosuke Okuda, Yuki Kajiwara, K. Terashima","doi":"10.1109/VLSI-DAT.2014.6834940","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834940","url":null,"abstract":"For past 10 years Advanced Driving Assistance System (ADAS) has rapidly grown. Recently not only luxury cars but some entry level cars are equipped with ADAS applications, such as Automated Emergency Braking System (AEBS). The European New Car Assessment Programme (EuroNCAP) announced its introduction of AEBS test from 2014, which will accelerate the penetration of ADAS in Europe. Also DARPA challenge started from 2004 accelerated the research for autonomous driving. Several OEMs and universities have demonstrated autonomous driving cars. This paper gives a brief survey of technical trend of ADAS and autonomous driving focusing on algorithms actually used for autonomous driving prototype cars.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115742438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 151
Advancing foundry technology with scaling and innovations 推动铸造技术的规模化和创新
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839696
Shien-Yang Wu, C. Y. Lin, S. Yang, J. Liaw, J. Cheng
{"title":"Advancing foundry technology with scaling and innovations","authors":"Shien-Yang Wu, C. Y. Lin, S. Yang, J. Liaw, J. Cheng","doi":"10.1109/VLSI-TSA.2014.6839696","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839696","url":null,"abstract":"Being the dedicated IC foundry, TSMC provides a complete portfolio of technologies covering leading-edge technology, specialty technology, and 3D IC system integration technology to fulfill customer product needs in various market segments. While the leading-edge CMOS technology continues to extend Moore's law as a driver for business growth, More-than-Moore specialty technology leverages the logic technology platform with value-added components to enable various functionalities for a wide range of applications. In this paper, the evolution of advanced CMOS technology is reviewed. Challenges in scaling transistor, SRAM and interconnect are discussed. Examples of specialty technology will also be illustrated.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124841002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Series resistance and mobility in mechanically-exfoliated layered transition metal dichalcogenide MOSFETs 机械剥离层状过渡金属二硫化物mosfet的串联电阻和迁移率
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839668
A. Sachid, Hui Fang, A. Javey, C. Hu
{"title":"Series resistance and mobility in mechanically-exfoliated layered transition metal dichalcogenide MOSFETs","authors":"A. Sachid, Hui Fang, A. Javey, C. Hu","doi":"10.1109/VLSI-TSA.2014.6839668","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839668","url":null,"abstract":"We show that transmission line method, where a set of devices are used, does not always correctly estimate series resistance of mechanically-exfoliated transition metal dichalcogenide MOSFETs. We calculate series resistance and carrier mobility from current-voltage characteristics of a single device. We show that series resistance should be considered for accurate mobility calculation even for long channel devices.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126356693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design for reliability for low power digital circuits 低功耗数字电路的可靠性设计
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839638
S. Kalpat
{"title":"Design for reliability for low power digital circuits","authors":"S. Kalpat","doi":"10.1109/VLSI-TSA.2014.6839638","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839638","url":null,"abstract":"Summary form only given. Lower power digital circuits in cellular phones, laptop or tablet computers have critical power consumption limitations. Power consumption at process corners can vary as much as 50%. In order to optimize high-speed logic circuit designs for low power needs, we need to accurately predict device to product aging across process, temperature and voltage corners. In this talk, we focus on the impact of BTI aging at corners, the Fmax guardband and its trade-off with power and performance.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132266284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study of the programming sequence induced back-pattern effect in split-page 3D vertical-gate (VG) NAND flash 分页三维垂直栅极NAND闪存中编程序列诱导背纹效应的研究
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839661
Wei-Chen Chen, H. Lue, Kuo-Pin Chang, Y. Hsiao, C. Hsieh, Y. Shih, Chih-Yuan Lu
{"title":"Study of the programming sequence induced back-pattern effect in split-page 3D vertical-gate (VG) NAND flash","authors":"Wei-Chen Chen, H. Lue, Kuo-Pin Chang, Y. Hsiao, C. Hsieh, Y. Shih, Chih-Yuan Lu","doi":"10.1109/VLSI-TSA.2014.6839661","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839661","url":null,"abstract":"For the first time the programming sequence induced array back-pattern effect is studied in a fully integrated split-page 3D vertical gate (VG) NAND Flash test chip. It is found that when programming of WL's starts from the source side it shows a wider programmed Vt (PV) distribution. It is clarified that when many WL's are programmed in the NAND string, the array loading resistance greatly increases, leading to the Vth shift for the earlier-programmed cells which is called the back-pattern effect. Our model indicates that the major mechanism comes from the decreased virtual drain potential of the selected WL when drain-side other WL's are programmed. In order to overcome the back-pattern effect, we propose a “by-page” programming method, where every page is programmed from drain (BL) side toward source side. It shows great improvements in PV distribution.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133679894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Dopant deactivation: A new challenge in sub-20nm scaled FinFETs 掺杂失活:亚20nm尺度finfet的新挑战
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839650
P. Debashis, S. Mittal, S. Lodha, U. Ganguly
{"title":"Dopant deactivation: A new challenge in sub-20nm scaled FinFETs","authors":"P. Debashis, S. Mittal, S. Lodha, U. Ganguly","doi":"10.1109/VLSI-TSA.2014.6839650","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839650","url":null,"abstract":"Recently, dopant deactivation (DD) based resistance increase in Si nanowires surrounded by low-k insulator has been experimentally demonstrated. Source/drain extension confined by low-k spacer in scaled fins for sub-20 nm FinFET are susceptible to such series resistance increase due to DD. In this paper, we implement DD into experimentally calibrated TCAD simulations of FinFETs and analyze the impact of DD on device performance with scaling for the first time. We show that the performance advantage with scaling is highly degraded in sub-20 nm gate length node (e.g. at 8 nm node the on-current degrades by more than 50% by adding DD correction). We further propose an optimal high-k spacer due to a DD mitigation vs. gate capacitance reduction trade-off (contrary to the present trend of spacer k-minimization based on only capacitance reduction considerations). We demonstrate that optimal higher-k spacer dielectric improves performance for technology nodes from 22 nm to 8 nm, e.g. optimized spacer can lead to 116% increase in ON current and 30% reduction in intrinsic delay for 8 nm FinFET compared to low-k spacers. In fact, optimized high-k spacer can restore FinFET performance to DD-uncorrected prediction levels at 8 nm node.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"48 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133119978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dielectric defects controlling instability in InGaAs n-MOSFETs with Al2O3/ZrO2 gate stack Al2O3/ZrO2栅层InGaAs n- mosfet的介电缺陷控制不稳定性
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839678
S. Deora, G. Bersuker, W. Loh, K. Matthews, C. Hobbs, P. Kirsch
{"title":"Dielectric defects controlling instability in InGaAs n-MOSFETs with Al2O3/ZrO2 gate stack","authors":"S. Deora, G. Bersuker, W. Loh, K. Matthews, C. Hobbs, P. Kirsch","doi":"10.1109/VLSI-TSA.2014.6839678","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839678","url":null,"abstract":"Instability under positive bias stress (DC and AC) in InGaAs channel nMOSFETs with a a 1nmAl<sub>2</sub>O<sub>3</sub>/5nmZrO<sub>2</sub> gate stack is studied. It is determined that the threshold voltage shift (ΔV<sub>T</sub>) during stress is primarily caused by a recoverable electron trapping at pre-existing defects, which are located pre-dominantly in the Al<sub>2</sub>O<sub>3</sub> interfacial layer (IL). Generation of new electron trapping defects is found to occur in the IL, in the region close to the substrate, while trap generation in the high-k dielectric is negligible. The ΔV<sub>T</sub> recovery impacts the degradation dependency on the stress duty cycle and frequency.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131736914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GaAs foundry technologies 砷化镓铸造技术
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839698
Yu-Chi Wang
{"title":"GaAs foundry technologies","authors":"Yu-Chi Wang","doi":"10.1109/VLSI-TSA.2014.6839698","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839698","url":null,"abstract":"GaAs wafer foundry has become an integral part of the RF/microwave semiconductor supply chain. A credible GaAs foundry has to establish its internal capability on developing cutting-edge technologies to meet the fast increasing product performance requirements in both mobile and infrastructure markets. Flip-chip bumping process, BiHEMT, mmW pHEMT, and high power GaN HEMT are clearly the critical technologies taking the microwave/mmW products toward higher performance, greater bandwidth, and higher power with smaller form factors.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"404 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122943138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analog power and specialty technologies 模拟电源和专业技术
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839700
Kurt Huang
{"title":"Analog power and specialty technologies","authors":"Kurt Huang","doi":"10.1109/VLSI-TSA.2014.6839700","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839700","url":null,"abstract":"Summary form only given. When the first iPhone introduced to the world in 2007, it stimulated the demand of personal electronic devices to a different level. With simple human-machine interfaces, modern smartphone has enabled a lot more persons to use electronic devices. As computing paradigms migrate from desktop to mobile, technology requirements differ. Performance driven consideration was overridden by power. Going forward, driven by immersion experience needs of IoT, sensing the environment and responding correctly under extreme power budget become the purpose of technology. Specialty technology, such as eNVM, RF, MEMS/sen sor and power management etc., become more important than ever. We will discuss about UMC strategy on specialty technologies in this paper.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"308 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127565063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
N-type doping of carbon nanotube transistors using yttrium oxide (Y2Ox) 用氧化钇掺杂碳纳米管晶体管的n型
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI: 10.1109/VLSI-TSA.2014.6839667
L. Liyanage, G. Pitner, Xiaoqing Xu, H. Wong
{"title":"N-type doping of carbon nanotube transistors using yttrium oxide (Y2Ox)","authors":"L. Liyanage, G. Pitner, Xiaoqing Xu, H. Wong","doi":"10.1109/VLSI-TSA.2014.6839667","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839667","url":null,"abstract":"We present a novel, VLSI compatible technique to fabricate n-type carbon nanotube (CNT) transistors using yttrium oxide as gate dielectric. Wafer-scale, aligned CNT transistors with yttrium oxide (Y<sub>2</sub>O<sub>x</sub>) dielectrics exhibit n-type behavior with I<sub>on</sub>/I<sub>off</sub> of 10<sup>6</sup> and subthreshold slope of 95 mV/dec. Controlled, slow evaporation of yttrium (Y) forms a smooth oxide surface that has excellent wetting to CNTs which consistently gives rise to strong n-type behavior in CNT transistors.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131454837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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