Dopant deactivation: A new challenge in sub-20nm scaled FinFETs

Abstract

Recently, dopant deactivation (DD) based resistance increase in Si nanowires surrounded by low-k insulator has been experimentally demonstrated. Source/drain extension confined by low-k spacer in scaled fins for sub-20 nm FinFET are susceptible to such series resistance increase due to DD. In this paper, we implement DD into experimentally calibrated TCAD simulations of FinFETs and analyze the impact of DD on device performance with scaling for the first time. We show that the performance advantage with scaling is highly degraded in sub-20 nm gate length node (e.g. at 8 nm node the on-current degrades by more than 50% by adding DD correction). We further propose an optimal high-k spacer due to a DD mitigation vs. gate capacitance reduction trade-off (contrary to the present trend of spacer k-minimization based on only capacitance reduction considerations). We demonstrate that optimal higher-k spacer dielectric improves performance for technology nodes from 22 nm to 8 nm, e.g. optimized spacer can lead to 116% increase in ON current and 30% reduction in intrinsic delay for 8 nm FinFET compared to low-k spacers. In fact, optimized high-k spacer can restore FinFET performance to DD-uncorrected prediction levels at 8 nm node.