分页三维垂直栅极NAND闪存中编程序列诱导背纹效应的研究

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2014-04-28 DOI:10.1109/VLSI-TSA.2014.6839661

Wei-Chen Chen, H. Lue, Kuo-Pin Chang, Y. Hsiao, C. Hsieh, Y. Shih, Chih-Yuan Lu

{"title":"分页三维垂直栅极NAND闪存中编程序列诱导背纹效应的研究","authors":"Wei-Chen Chen, H. Lue, Kuo-Pin Chang, Y. Hsiao, C. Hsieh, Y. Shih, Chih-Yuan Lu","doi":"10.1109/VLSI-TSA.2014.6839661","DOIUrl":null,"url":null,"abstract":"For the first time the programming sequence induced array back-pattern effect is studied in a fully integrated split-page 3D vertical gate (VG) NAND Flash test chip. It is found that when programming of WL's starts from the source side it shows a wider programmed Vt (PV) distribution. It is clarified that when many WL's are programmed in the NAND string, the array loading resistance greatly increases, leading to the Vth shift for the earlier-programmed cells which is called the back-pattern effect. Our model indicates that the major mechanism comes from the decreased virtual drain potential of the selected WL when drain-side other WL's are programmed. In order to overcome the back-pattern effect, we propose a “by-page” programming method, where every page is programmed from drain (BL) side toward source side. It shows great improvements in PV distribution.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Study of the programming sequence induced back-pattern effect in split-page 3D vertical-gate (VG) NAND flash\",\"authors\":\"Wei-Chen Chen, H. Lue, Kuo-Pin Chang, Y. Hsiao, C. Hsieh, Y. Shih, Chih-Yuan Lu\",\"doi\":\"10.1109/VLSI-TSA.2014.6839661\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For the first time the programming sequence induced array back-pattern effect is studied in a fully integrated split-page 3D vertical gate (VG) NAND Flash test chip. It is found that when programming of WL's starts from the source side it shows a wider programmed Vt (PV) distribution. It is clarified that when many WL's are programmed in the NAND string, the array loading resistance greatly increases, leading to the Vth shift for the earlier-programmed cells which is called the back-pattern effect. Our model indicates that the major mechanism comes from the decreased virtual drain potential of the selected WL when drain-side other WL's are programmed. In order to overcome the back-pattern effect, we propose a “by-page” programming method, where every page is programmed from drain (BL) side toward source side. It shows great improvements in PV distribution.\",\"PeriodicalId\":403085,\"journal\":{\"name\":\"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-TSA.2014.6839661\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-TSA.2014.6839661","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

首次在完全集成的分页三维垂直栅极NAND闪存测试芯片上研究了编程序列引起的阵列背纹效应。研究发现，当从源侧开始编程时，编程后的Vt (PV)分布更宽。当在NAND串中编程许多WL时，阵列加载阻力大大增加，导致先前编程的单元发生第v次移位，称为反向模式效应。我们的模型表明，当对漏侧其他WL进行编程时，主要机制来自所选WL的虚拟漏势降低。为了克服反向模式效应，我们提出了一种“逐页”编程方法，其中每个页面从漏端(BL)向源端编程。它显示了PV分布的巨大改进。

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Study of the programming sequence induced back-pattern effect in split-page 3D vertical-gate (VG) NAND flash

For the first time the programming sequence induced array back-pattern effect is studied in a fully integrated split-page 3D vertical gate (VG) NAND Flash test chip. It is found that when programming of WL's starts from the source side it shows a wider programmed Vt (PV) distribution. It is clarified that when many WL's are programmed in the NAND string, the array loading resistance greatly increases, leading to the Vth shift for the earlier-programmed cells which is called the back-pattern effect. Our model indicates that the major mechanism comes from the decreased virtual drain potential of the selected WL when drain-side other WL's are programmed. In order to overcome the back-pattern effect, we propose a “by-page” programming method, where every page is programmed from drain (BL) side toward source side. It shows great improvements in PV distribution.

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Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

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