A high density Twin-Gate OTP cell in pure 28nm CMOS process

Abstract

A high density high-k gate dielectric breakdown OTP cell with a self-aligned twin-gate isolation in pure 28nm HKMG process is demonstrated. With a merged spacer isolation formed by two tiny metal gates, the OTP cells can be well isolated with an ultra small cell size of 0.0441μm2 in pure 28nm CMOS logic process. The Twin-Gate OTP memory adopts low voltage high-k dielectric breakdown mechanism to obtain 104 times of On/Off ratio by a low program voltage of 4V in 20μs. A tiny and excellent Twin-Gate isolation with wide program and temperature margins has been successfully achieved in this OTP cell. Superior disturbs immunity and data retention further support the new logic OTP cell to be a promising solution in advanced logic NVM applications.