D. Triyoso, S. Chu, K. Seidel, W. Weinreich, K. Yiang, M. Nolan, D. Brunco, J. Rinderknecht, D. Utess, C. Kyono, R. Miller, J. Park, Lili Cheng, M. Liebau, Patrick Lomtscher, R. Fox
{"title":"Understanding the materials, electrical and reliability impact of Al-addition to ZrO2 for BEOL compatible MIM capacitors","authors":"D. Triyoso, S. Chu, K. Seidel, W. Weinreich, K. Yiang, M. Nolan, D. Brunco, J. Rinderknecht, D. Utess, C. Kyono, R. Miller, J. Park, Lili Cheng, M. Liebau, Patrick Lomtscher, R. Fox","doi":"10.1109/VLSI-TSA.2014.6839694","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839694","url":null,"abstract":"As operating frequency and circuit density of VLSI systems continue to increase, the L*di/dt induced voltage fluctuations in the power grid increasingly becomes a source of voltage/timing problems. On-chip decoupling capacitors, placed in close proximity to the power grid conductors, can offset parasitic inductances and thereby reduce the high frequency noise. High capacitance density MIM capacitors, placed between the last two metal layers, have been shown to be effective in achieving on-chip decoupling in high performance processors. There have been many reports in the literature on the use of high-k material such as Ta2O5, HfO2, ZrO2 for MIM capacitors [1-5]. A large number of reports of high-k MIM are focused on DRAM rather than decoupling capacitors applications [2-4]. One important difference between the DRAM capacitor module and decoupling capacitors is the thermal budget requirement. DRAM capacitors allow a higher thermal budget (~700°C) compared to embedded decoupling capacitors which must meet the BEOL thermal budget requirement (~400°C). We have recently reported an improved reliability by addition of Al into ZrO2 [6]. In this work, we report detailed material, electrical and further reliability characterization of ZrO2-based MIM capacitor capable of meeting stringent reliability requirement while maintaining compatibility with the backend processing thermal budget. A capacitor with >20fF/μm2 capacitance density and leakage current density <;100nA/cm2 meeting lifetime target (operated on both polarities) is demonstrated.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130255655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Ngai, R. Clark, D. Veksler, K. Matthews, E. Bersch, D. Gilmer, G. Bersuker, R. Hill, C. Hobbs, K. Tapily, C. Wajda, S. Consiglio, T. Burroughs, S. Vivekanand, V. Kaushik, G. Leusink, P. Kirsch
{"title":"Mechanistic understanding of mobility degradation on gate-last ZrO2 with medium thermal budget annealing","authors":"T. Ngai, R. Clark, D. Veksler, K. Matthews, E. Bersch, D. Gilmer, G. Bersuker, R. Hill, C. Hobbs, K. Tapily, C. Wajda, S. Consiglio, T. Burroughs, S. Vivekanand, V. Kaushik, G. Leusink, P. Kirsch","doi":"10.1109/VLSI-TSA.2014.6839649","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839649","url":null,"abstract":"In this paper, we provide a mechanistic understanding of mobility degradation of gate-last ZrO2 subjected to medium thermal budget annealing. We find that high-k post deposition anneal (PDA) even at modest temperatures can improve the interfacial layer (IL) and bulk oxide, but mobility suffers. The mechanism for this mobility degradation is the enhanced remote Coulomb scattering from nonstoichiometric ZrOx region near the IL. The high-k PDA, even at moderate temperature, enables oxygen gettering of the IL and deprives oxygen from ZrO2 near the IL, which results in the accumulation of defects/traps in the region near ZrO2/IL interface. This enhances remote Coulomb scattering due to the high concentration of oxide traps and their close proximity to the conductance channel. Consequently, mobility is degraded even though IL and bulk oxide are improved.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127453008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Ahn, Seyoung Kim, T. Gokmen, O. Dial, M. Ritter, H. Wong
{"title":"Temperature-dependent studies of the electrical properties and the conduction mechanism of HfOx-based RRAM","authors":"C. Ahn, Seyoung Kim, T. Gokmen, O. Dial, M. Ritter, H. Wong","doi":"10.1109/VLSI-TSA.2014.6839685","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839685","url":null,"abstract":"The conduction mechanism of HfOx-based RRAM is investigated by analyzing the I-V characteristics of HfOx-based RRAM devices at different temperatures ranging from 350 K down to 40 K. Electrical conduction of RRAM is found to be strongly dependent on the resistance state of the device, electric field, and temperature. At relatively high electric field (E > 3 MV/cm), Poole-Frenkel conduction explains our measured temperature dependence at limited temperature (T > 200 K) and bias ranges while trap-assisted tunneling accounts for the temperature-insensitive conduction regime (T <; 100 K). It is also concluded that the more resistive RRAM device shows weaker dependence on temperature.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132695756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Body-bias effect in SOI FinFET for low-power applications: Gate length dependence","authors":"A. Sachid, S. Khandelwal, C. Hu","doi":"10.1109/VLSI-TSA.2014.6839655","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839655","url":null,"abstract":"We study the gate length dependence of body-bias effect in SOI FinFETs. Using measurements and simulations we show that body-bias effect is enhanced as the gate length is decreased. We study the impact of channel doping and device geometry on body-bias effect.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115598576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Cong, Dedong Han, D. Shan, Yu Tian, F. Huang, Suoming Zhang, Zhuofa Chen, Jing Wu, N. Zhao, F. Zhao, Junchen Dong, Shenmin Zhang, Xing Zhang, Yi Wang
{"title":"High mobility transparent Al-Sn-Zn-O thin film transistors fabricated at low temperature","authors":"Y. Cong, Dedong Han, D. Shan, Yu Tian, F. Huang, Suoming Zhang, Zhuofa Chen, Jing Wu, N. Zhao, F. Zhao, Junchen Dong, Shenmin Zhang, Xing Zhang, Yi Wang","doi":"10.1109/VLSI-TSA.2014.6839671","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839671","url":null,"abstract":"Fully-transparent inverted-staggered Aluminum and Tin co-doped ZnO (ATZO) thin film transistors (TFTs) have been fabricated by RF magnetron sputtering on glass substrate at low temperature. The characteristics of ATZO TFTs fabricated at various partial pressures of oxygen are studied. The ATZO TFTs demonstrate excellent performance, including a high field effect mobility of 145.33 cm2/Vs, a threshold voltage of 1.71 V, a subthreshold swing of 0.22 V/dec and an on-to-off current ratio of 7.5×107.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125751688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Inorganic-organic hybrid resistive switching memory with high uniformity and multilevel operation","authors":"Yefan Liu, Yimao Cai, Qiang Li, Yue Pan, Zongwei Wang, Ru Huang","doi":"10.1109/VLSI-TSA.2014.6839676","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839676","url":null,"abstract":"Poor uniformity of switching parameters has become a main obstacle hindering the real application of single-polymer organic RRAM devices. In this paper, target to solve this issue, an HfOx/parylene hybrid RRAM device has been proposed and experimentally investigated. Measurement data reveals that the switching parameters uniformity of hybrid devices is dramatically improved compared to pure parylene RRAM devices. In addition, hybrid devices show the capability of low-voltage operation (Vset~-2V, Vreset~0.6V) and high on/off current ratio (>1000). Due to the high uniformity and large on/off ratio, the multilevel storage ability with good retention of this hybrid device was experimentally demonstrated.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125815126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Yoshida, Keping Han, P. Hsu, Matthew Beach, Xinliang Lu, R. Hung, D. Mao, Hao Chen, Wei Tang, Y. Lei, Jing Zhou, A. Noori, M. Jin, Kun Xu, A. Phatak, Shiyu Sun, S. Hassan, S. Gandikota, Chorng-Ping Chang, A. Brand
{"title":"Threshold voltage tuning by metal gate work function modulation for 10 nm CMOS integration and beyond","authors":"N. Yoshida, Keping Han, P. Hsu, Matthew Beach, Xinliang Lu, R. Hung, D. Mao, Hao Chen, Wei Tang, Y. Lei, Jing Zhou, A. Noori, M. Jin, Kun Xu, A. Phatak, Shiyu Sun, S. Hassan, S. Gandikota, Chorng-Ping Chang, A. Brand","doi":"10.1109/VLSI-TSA.2014.6839647","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839647","url":null,"abstract":"This paper describes a novel scheme of metal gate integration to achieve precise threshold voltage (VTH) control and multiple VTH, by using metal composition and ion implantation (I/I) into work function metal (WFM). Moreover, WFM full fill is demonstrated with in situ barrier metal to satisfy the conductance requirement of sub-10 nm node gate.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129049894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Influence of fin-width lateral variations of a FinFET","authors":"C. Prawoto, M. Cheralathan, M. Chan","doi":"10.1109/VLSI-TSA.2014.6839651","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839651","url":null,"abstract":"We have presented that, in terms of subthreshold operation, IOFF, SS and DIBL are improved in response to higher degree of lateral thickness non-uniformity. We have shown that the linearly varying film thickness of a FinFET introduces effects comparable to small variations in overall thickness. To address the non-uniformity, a correction factor for the overall thickness based on IOFF could be employed. Due to its non-trivial effects, this thickness variation angle should be considered as a parameter in FinFET modeling in order to capture a more accurate behavior, instead of only taking the average thickness.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127612946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abhishek A. Sharma, M. Noman, M. Skowronski, J. Bain
{"title":"High-speed in-situ pulsed thermometry in oxide RRAMs","authors":"Abhishek A. Sharma, M. Noman, M. Skowronski, J. Bain","doi":"10.1109/VLSI-TSA.2014.6839687","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839687","url":null,"abstract":"We present an in-situ temperature characterization technique applicable to forming as well as switching in oxide RRAM. This work provides unambiguous evidence that the switching event in these oxide systems includes a thermal event involving temperature excursions of hundreds of °C within a 10 nm filament. The applicability of this technique to as-fabricated devices makes it distinct from previous extraction methodologies that make use of specialized test structures that may have very different thermal environment compared to functional memory blocks. One of the key contributions of this technique is the scalability of this technique with changing size of the conducting filament.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127993717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Dielacher, M. Tiebout, R. Lachner, H. Knapp, K. Aufinger, W. Sansen
{"title":"SiGe BiCMOS technology and circuits for active safety systems","authors":"F. Dielacher, M. Tiebout, R. Lachner, H. Knapp, K. Aufinger, W. Sansen","doi":"10.1109/VLSI-TSA.2014.6839643","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839643","url":null,"abstract":"This paper provides an overview of the features and capabilities of state-of-the-art SiGe devices and BiCMOS technology for applications such as high-data-rate communications and pro-active safety systems like car-radar, identification and e-safety. The capabilities offered by SiGe-BiCMOS and microwave packaging enable the integration of complete transceivers on a chip or in a package even including the antenna. The criteria and trade-off's for the technology selection and system partitioning are described in the introduction. In addition to the electrical components performance, major criteria are addressed such as high reliability, long lifetime and high yield fabrication. Advanced packaging technologies are addressed as well, including embedded passive components and package co-design. Existing circuit design examples and future solutions for 77 GHz automotive radar are presented, followed by a multichannel receiver and a multichannel transmitter for mm-wave people scanners for airport security.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"465 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133133769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}