Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)最新文献

{"title":"Designer Ge quantum dots Coulomb blockade thermometry","authors":"I. Chen, C. C. Wang, P. W. Li","doi":"10.1109/VLSI-TSA.2014.6839670","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839670","url":null,"abstract":"A Coulomb blockade (CB) thermometer has been experimentally demonstrated based on the temperature dependence of a Ge quantum-dot (QD) single-hole transistor (SHT). The Ge-QD SHT features distinctive current peaks/plateaus, sharp differential conductance (G_D) dips up to temperature 120K. The full-width-at-half minimum, V_1/2, of the G_D dips directly scale with temperature following the material parameter-independent equation of eV_1/2 ~ 5.44k_BT, providing the primary thermometric quantity. Also the depths of the G_D dips increases with 1/k_BT as expected from CB theory of ΔG_D/G_D0 = E_C/6k_BT. This experimental demonstration indicates that our Ge-QD SHT offers an effective building block for ultrasensitive CB primary thermometers with the detection temperature as high as 115K.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130786943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Attomolar streptavidin and pH, low power sensor based on 3D vertically stacked SiNW FETs","authors":"E. Buitrago, M. Fernandez-Bolaños, Y. Georgiev, Yu-tong Ran, O. Lotty, J. Holmes, A. Nightingale, A. Ionescu","doi":"10.1109/VLSI-TSA.2014.6839691","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839691","url":null,"abstract":"3D vertically stacked silicon nanowire (SiNW) field effect transistors (FET) with high density arrays (up to 7×20) of fully depleted and ultra-thin (15-30 nm) suspended channels were fabricated by a top-down CMOS compatible process on silicon on insulator (SOI). The channels can be wrapped by conformal high-κ gate dielectrics (HfO2) and their conductivity can be excellently controlled either by a reference electrode or by three local gates; a backgate (BG) and two symmetrical Pt side-gates (SG) offering unique sensitivity tuning. Such 3D structure has been (3-Aminopropyl)-triethoxysilane (APTES) functionalized and biotynilated for pH and streptavidin (protein) sensing, respectively. An ultra-low concentration of 17 aM of streptavidin was measured, the lowest ever reported in literature. Extremely high quasi-exponential drain current responses (ΔId/pH) of ~0.70 dec/pH were measured for structures with APTES functionalized SiO2 gate dielectrics when operated in the subthreshold regime. Also, high drain current responses > 20 μA/pH and high sensitivities (S ~ 95%) were measured for structures with a native oxide gate dielectrics when operated in the strong-inversion regime.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114180412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 4ns, 0.9V write voltage embedded perpendicular STT-MRAM fabricated by MTJ-Last process","authors":"K. Ikegami, H. Noguchi, C. Kamata, M. Amano, K. Abe, K. Kushida, E. Kitagawa, T. Ochiai, N. Shimomura, A. Kawasumi, H. Hara, J. Ito, S. Fujita","doi":"10.1109/VLSI-TSA.2014.6839663","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839663","url":null,"abstract":"We evaluated embedded perpendicular spin transfer torque magnetic random access memory (STT-MRAM) performance fabricated by magnetic tunnel junction (MTJ) -“Last process”, which is able to expand material and structural design space of CMOS and MTJ, by SPICE simulation and test chip measurement. By the post-layout simulation, we show that the delay increase by parasitics, which originates from fabricating MTJ on the upper metal layer is below 50ps and negligible for most applications. And from the test chip measurement, we demonstrated switching operation as fast as 4ns, below 1V for STT-MRAM.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127486880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Foundry technology for RF and high performance analog applications","authors":"P. Hurwitz, S. Chaudhry, E. Preisler, R. Kanawati, M. Racanelli","doi":"10.1109/VLSI-TSA.2014.6839697","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839697","url":null,"abstract":"The requirements for silicon foundry technology serving the RF / mixed signal and high performance analog (HPA) market are very different from those intended for mostly digital designs. RF / HPA applications require a rich set of features in a modular platform with accurate RF models for first-pass design success in demanding applications that stress speed, voltage and noise requirements. In this paper we present examples of such technologies focusing on two areas of particular recent interest: silicon technology for the front-end module of wireless handsets and high-speed SiGe BiCMOS technology serving high-speed networks and mmWave wireless applications.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127771248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Monolithic graphene frequency multiplier working at 10GHz range","authors":"L. Hongming, Huaqiang Wu, Jinbiao Liu, J. Niu, Yu Jiahan, Can Huang, Junfeng Li, Qiuxia Xu, Xiao-Shan Wu, H. Qian","doi":"10.1109/VLSI-TSA.2014.6839669","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839669","url":null,"abstract":"A high-performance monolithically integrated graphene frequency multiplier working at 10 GHz range is demonstrated with novel implementation method. A CMOS compatible two-layer-routing process is proposed to fabricate passive elements, interconnects and buried gate/source/drain regions on 8\" wafers. This is followed by large-scale monolayer graphene transfer to form graphene ICs. The frequency multiplier circuit features a 3dB bandwidth of record high 4GHz. The conversion gain reaches -26dB.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121238459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low current cross-point memory using gadolinium-oxide switching material","authors":"D. Jana, S. Maikap, Y. Chen, J. Yang","doi":"10.1109/VLSI-TSA.2014.6839686","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839686","url":null,"abstract":"Low current cross-point memory using gadolinium-oxide switching material in an IrOx/GdOx/W structure has been investigated for the first time. Memory device shows low current bipolar resistive switching phenomena and self-compliance phenomena as well, repeatable switching cycles, good uniformity, long program/erase endurance of >60k every cycles, and good data retention of >104 s at a low CC of 50 μA.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"09 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116383983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A TSV-based heterogeneous integrated neural-signal recording device with microprobe array","authors":"Lei-Chun Chou, Shih-Wei Lee, Chuan-An Cheng, Po-Tsang Huang, Chih-Wei Chang, Cheng-Hao Chiang, Shang-Lin Wu, C. Chuang, J. Chiou, W. Hwang, Chung-Hsi Wu, Kuo-Hua Chen, C. Chiu, H. Tong, Kuan-Neng Chen","doi":"10.1109/VLSI-TSA.2014.6839692","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839692","url":null,"abstract":"Highly integrated and miniaturized neural sensing microsystems are crucial for brain function investigation and neural prostheses realization. This paper presents a TSV-based heterogeneous integrated neural-signal recording device with microprobe array. By TSV, microprobe array and CMOS circuit make connection on the opposite sides of the chip. By measurement results on electrical characteristics of devices and TSV, this recording device is ready for bio-medical applications.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128384558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fluctuation in drain induced barrier lowering (DIBL) for FinFETs caused by granular work function variation of metal gates","authors":"T. Matsukawa, K. Fukuda, Y. Liu, K. Endo, J. Tsukada, Y. Ishikawa, H. Yamauchi, S. O'Uchi, S. Migita, W. Mizubayashi, Y. Morita, H. Ota, M. Masahara","doi":"10.1109/VLSI-TSA.2014.6839648","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839648","url":null,"abstract":"Fluctuation in drain induced barrier lowering (DIBL) has been investigated in detail for FinFETs with regard to work function variation (WFV) in the metal gates (MGs). The FinFETs with a polycrystalline TiN MG exhibit significantly larger fluctuation in DIBL than that for an amorphous TaSiN MG because of the WFV. The granular WFV of TiN was modeled using 3D TCAD simulation. By reproducing the DIBL fluctuation caused by the WFV, mechanism of how the WFV causes the DIBL fluctuation is discussed.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130995916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploring technology solution paths for expaned 3D devices, interconnects and system integrations beyond TSV","authors":"Herb Huang","doi":"10.1109/VLSI-TSA.2014.6839702","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839702","url":null,"abstract":"Summary form only given. As key front-end, middle-end and backend module process enablers are approaching or achieve maturity, TSV technology has been successfully implemented onto certain advanced commercial IC products. Intensive effort is being made currently to explore further deployment of TSV-based 3D interconnect solutions for various advancing SOC and SiP offerings. Among various well demonstrated architectures, only a few are taken as both cost and performance justifiable solutions for practical implementation into commercial products. TSV-based 2.5D SiP for high performance FPGA and TSV-based stacked memory IC are well recognized ones of this kind. While the product realization of TSV wide I/O is delayed further from previous high expectation in the industry, other TSV-based active interposer architectures are demonstrated technically and economically viable, surprisingly forseen to enter commercial deployment even before TSV wide I/O. A low density but embedded TSV technology, illustrated in the paper, is proven as a cost-effective and technically viable solution for a wide range of ultra thin SiPs of MEMS-based smart sensor products. In parallel to applying TSV as the system integration solution for cross-chip interconnects, extrapolating the core concepts of 3D silicon re-construction is fanning out to a broader range of equally exciting technological innovations and products, such as 3D NAND and DRAM. Again, 3D IC is not just simply employing TSV as the alternative interconnect solution, rather a broad spectrum of innovative re-constructions of silicon devices, interconnects and system integrations in one or multiple combinations beyond conventional 2D integrated circuits design and fabrication methodology. There lies great potential and excitement for new devices, IC products and system packages with both performance and cost benefits, to design, develop and commercialize in coming years as illustrated in the paper. A systematic approach to exploring and deploying the core concepts of 3D IC beyond TSV is concluded and proposed.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132030408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Technologies and challenges of fine-pitch backside via-last 3DIC TSV process integration and its electrical characteristics and system applications","authors":"E. Chen, T. Hsu, Cha-Hsin Lin, P. Tzeng, Chung-Chih Wang, Shang-Chun Chen, Jui-Chin Chen, Chien-Chou Chen, Y. Hsin, Po-Chih Chang, Yiu-Hsiang Chang, Shin-Chiang Chen, Yu-Ming Lin, S. Liao, C. Ko, C. Zhan, Hsiang-Hung Chang, C. Chien, Yung-Fa Chou, D. Kwai, W. Lo, T. Ku, M. Kao","doi":"10.1109/VLSI-TSA.2014.6839695","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839695","url":null,"abstract":"Technologies of fine-pitch backside via last 3DIC through silicon via (TSV) process are developed to be applied to the mass production of 3D IC products. The detailed process development key points and challenges are disclosed. The electrical data are also analyzed to check the TSV process. Also, its application in real 3DIC system is demonstrated to show the benefits of system form factor and frame rate.","PeriodicalId":403085,"journal":{"name":"Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134608415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}