K. Ikegami, H. Noguchi, C. Kamata, M. Amano, K. Abe, K. Kushida, E. Kitagawa, T. Ochiai, N. Shimomura, A. Kawasumi, H. Hara, J. Ito, S. Fujita
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引用次数: 12
Abstract
We evaluated embedded perpendicular spin transfer torque magnetic random access memory (STT-MRAM) performance fabricated by magnetic tunnel junction (MTJ) -“Last process”, which is able to expand material and structural design space of CMOS and MTJ, by SPICE simulation and test chip measurement. By the post-layout simulation, we show that the delay increase by parasitics, which originates from fabricating MTJ on the upper metal layer is below 50ps and negligible for most applications. And from the test chip measurement, we demonstrated switching operation as fast as 4ns, below 1V for STT-MRAM.